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Implement atomic_t<>::release
More relaxed store with release memory order
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Nekotekina
parent
50922faac9
commit
2b66abaf10
@ -4,7 +4,7 @@
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#include <functional>
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// Helper class, provides access to compiler-specific atomic intrinsics
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template<typename T, std::size_t Size = sizeof(T)>
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template <typename T, std::size_t Size = sizeof(T)>
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struct atomic_storage
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{
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static_assert(sizeof(T) <= 16 && sizeof(T) == alignof(T), "atomic_storage<> error: invalid type");
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@ -29,6 +29,11 @@ struct atomic_storage
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__atomic_store(&dest, &value, __ATOMIC_SEQ_CST);
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}
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static inline void release(T& dest, T value)
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{
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__atomic_store(&dest, &value, __ATOMIC_RELEASE);
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}
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static inline T exchange(T& dest, T value)
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{
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T result;
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@ -176,7 +181,7 @@ struct atomic_storage
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/* The rest: ugly MSVC intrinsics + inline asm implementations */
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template<typename T>
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template <typename T>
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struct atomic_storage<T, 1> : atomic_storage<T, 0>
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{
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#ifdef _MSC_VER
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@ -200,6 +205,12 @@ struct atomic_storage<T, 1> : atomic_storage<T, 0>
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_InterlockedExchange8((volatile char*)&dest, (char&)value);
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}
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static inline void release(T& dest, T value)
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{
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_ReadWriteBarrier();
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*(volatile char*)&dest = (char&)value;
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}
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static inline T exchange(T& dest, T value)
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{
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char r = _InterlockedExchange8((volatile char*)&dest, (char&)value);
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@ -232,7 +243,7 @@ struct atomic_storage<T, 1> : atomic_storage<T, 0>
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#endif
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};
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template<typename T>
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template <typename T>
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struct atomic_storage<T, 2> : atomic_storage<T, 0>
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{
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#ifdef _MSC_VER
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@ -256,6 +267,12 @@ struct atomic_storage<T, 2> : atomic_storage<T, 0>
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_InterlockedExchange16((volatile short*)&dest, (short&)value);
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}
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static inline void release(T& dest, T value)
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{
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_ReadWriteBarrier();
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*(volatile short*)&dest = (short&)value;
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}
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static inline T exchange(T& dest, T value)
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{
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short r = _InterlockedExchange16((volatile short*)&dest, (short&)value);
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@ -324,7 +341,7 @@ struct atomic_storage<T, 2> : atomic_storage<T, 0>
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#endif
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};
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template<typename T>
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template <typename T>
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struct atomic_storage<T, 4> : atomic_storage<T, 0>
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{
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#ifdef _MSC_VER
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@ -348,6 +365,12 @@ struct atomic_storage<T, 4> : atomic_storage<T, 0>
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_InterlockedExchange((volatile long*)&dest, (long&)value);
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}
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static inline void release(T& dest, T value)
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{
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_ReadWriteBarrier();
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*(volatile long*)&dest = (long&)value;
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}
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static inline T exchange(T& dest, T value)
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{
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long r = _InterlockedExchange((volatile long*)&dest, (long&)value);
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@ -423,7 +446,7 @@ struct atomic_storage<T, 4> : atomic_storage<T, 0>
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#endif
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};
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template<typename T>
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template <typename T>
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struct atomic_storage<T, 8> : atomic_storage<T, 0>
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{
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#ifdef _MSC_VER
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@ -447,6 +470,12 @@ struct atomic_storage<T, 8> : atomic_storage<T, 0>
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_InterlockedExchange64((volatile llong*)&dest, (llong&)value);
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}
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static inline void release(T& dest, T value)
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{
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_ReadWriteBarrier();
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*(volatile llong*)&dest = (llong&)value;
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}
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static inline T exchange(T& dest, T value)
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{
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llong r = _InterlockedExchange64((volatile llong*)&dest, (llong&)value);
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@ -525,7 +554,7 @@ struct atomic_storage<T, 8> : atomic_storage<T, 0>
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#endif
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};
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template<typename T>
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template <typename T>
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struct atomic_storage<T, 16> : atomic_storage<T, 0>
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{
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#ifdef _MSC_VER
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@ -550,6 +579,14 @@ struct atomic_storage<T, 16> : atomic_storage<T, 0>
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while (!_InterlockedCompareExchange128((volatile llong*)&dest, hi, lo, cmp));
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}
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static inline void release(T& dest, T value)
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{
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llong lo = *(llong*)&value;
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llong hi = *((llong*)&value + 1);
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llong cmp[2]{ *(volatile llong*)&dest, *((volatile llong*)&dest + 1) };
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while (!_InterlockedCompareExchange128((volatile llong*)&dest, hi, lo, cmp));
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}
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static inline T exchange(T& dest, T value)
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{
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llong lo = *(llong*)&value;
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@ -764,6 +801,12 @@ public:
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return rhs;
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}
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// Atomically write data with release memory order (faster on x86)
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void release(const type& rhs)
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{
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atomic_storage<type>::release(m_data, rhs);
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}
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// Atomically replace data with value, return previous data value
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type exchange(const type& rhs)
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{
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@ -543,11 +543,7 @@ void spu_recompiler_base::dispatch(spu_thread& spu, void*, u8* rip)
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// If code verification failed from a patched patchpoint, clear it with a single NOP
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if (rip)
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{
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#ifdef _MSC_VER
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*(volatile u64*)(rip) = 0x841f0f;
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#else
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__atomic_store_n(reinterpret_cast<u64*>(rip), 0x841f0f, __ATOMIC_RELAXED);
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#endif
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atomic_storage<u64>::release(*reinterpret_cast<u64*>(rip), 0x841f0f);
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}
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// Second attempt (recover from the recursion after repeated unsuccessful trampoline call)
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@ -580,7 +576,11 @@ void spu_recompiler_base::branch(spu_thread& spu, void*, u8* rip)
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// Overwrite jump to this function with jump to the compiled function
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const s64 rel = reinterpret_cast<u64>(func) - reinterpret_cast<u64>(rip) - 5;
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alignas(8) u8 bytes[8];
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union
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{
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u8 bytes[8];
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u64 result;
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};
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if (rel >= INT32_MIN && rel <= INT32_MAX)
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{
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@ -609,11 +609,7 @@ void spu_recompiler_base::branch(spu_thread& spu, void*, u8* rip)
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std::memset(bytes + 3, 0x00, 5);
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}
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#ifdef _MSC_VER
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*(volatile u64*)(rip) = *reinterpret_cast<u64*>(+bytes);
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#else
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__atomic_store_n(reinterpret_cast<u64*>(rip), *reinterpret_cast<u64*>(+bytes), __ATOMIC_RELAXED);
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#endif
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atomic_storage<u64>::release(*reinterpret_cast<u64*>(rip), result);
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}
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std::vector<u32> spu_recompiler_base::block(const be_t<u32>* ls, u32 entry_point)
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@ -245,12 +245,7 @@ public:
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void set_value(u32 value, bool count = true)
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{
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const u64 new_data = u64{count} << off_count | value;
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#ifdef _MSC_VER
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const_cast<volatile u64&>(data.raw()) = new_data;
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#else
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__atomic_store_n(&data.raw(), new_data, __ATOMIC_RELAXED);
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#endif
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data.release(u64{count} << off_count | value);
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}
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u32 get_value()
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@ -85,7 +85,7 @@ namespace vm
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if (!lock && lock.compare_and_swap_test(0, lock_info))
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{
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return &lock;
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}
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}
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}
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}
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}
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@ -256,7 +256,7 @@ namespace vm
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{
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const u64 value = lock;
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// Test beginning address
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// Test beginning address
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if (static_cast<u32>(value) > addr)
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{
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break;
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@ -295,7 +295,7 @@ namespace vm
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writer_lock::~writer_lock()
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{
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g_addr_lock.raw() = 0;
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g_addr_lock.release(0);
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g_mutex.unlock();
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}
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