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mirror of https://github.com/RPCS3/rpcs3.git synced 2025-02-23 06:40:49 +00:00

ARMv7: ADD*, LSL*, shifts fixed

This commit is contained in:
Nekotekina 2014-11-07 22:30:04 +03:00
parent 2fb0911e2a
commit 27c35174bc
5 changed files with 585 additions and 73 deletions

@ -90,6 +90,46 @@ void ARMv7Interpreter::ADD_IMM(const u32 data, const ARMv7_encoding type)
imm32 = (data & 0x1c0) >> 6;
break;
}
case T2:
{
d = n = (data & 0x700) >> 8;
imm32 = (data & 0xff);
break;
}
case T3:
{
d = (data & 0xf00) >> 8;
n = (data & 0xf0000) >> 16;
set_flags = (data & 0x100000);
imm32 = ThumbExpandImm((data & 0x4000000) >> 15 | (data & 0x7000) >> 4 | (data & 0xff));
if (d == 15 && set_flags)
{
throw "CMN (immediate)";
}
if (n == 13)
{
throw "ADD (SP plus immediate)";
}
break;
}
case T4:
{
d = (data & 0xf00) >> 8;
n = (data & 0xf0000) >> 16;
set_flags = false;
imm32 = (data & 0x4000000) >> 15 | (data & 0x7000) >> 4 | (data & 0xff);
if (n == 15)
{
throw "ADR";
}
if (n == 13)
{
throw "ADD (SP plus immediate)";
}
break;
}
case A1: throw __FUNCTION__;
default: throw __FUNCTION__;
}
@ -115,11 +155,75 @@ void ARMv7Interpreter::ADD_IMM(const u32 data, const ARMv7_encoding type)
void ARMv7Interpreter::ADD_REG(const u32 data, const ARMv7_encoding type)
{
bool set_flags = !CPU.ITSTATE;
u32 cond = CPU.ITSTATE.advance();
u32 d = 0;
u32 n = 0;
u32 m = 0;
auto shift_t = SRType_LSL;
u32 shift_n = 0;
switch (type)
{
case T1:
{
d = (data & 0x7);
n = (data & 0x38) >> 3;
m = (data & 0x1c0) >> 6;
break;
}
case T2:
{
n = d = (data & 0x80) >> 4 | (data & 0x7);
m = (data & 0x78) >> 3;
set_flags = false;
if (n == 13 || m == 13)
{
throw "ADD (SP plus register)";
}
break;
}
case T3:
{
d = (data & 0xf00) >> 8;
n = (data & 0xf0000) >> 16;
m = (data & 0xf);
set_flags = (data & 0x100000);
shift_t = DecodeImmShift((data & 0x30) >> 4, (data & 0x7000) >> 10 | (data & 0xc0) >> 6, &shift_n);
if (d == 15 && set_flags)
{
throw "CMN (register)";
}
if (n == 13)
{
throw "ADD (SP plus register)";
}
break;
}
case A1: throw __FUNCTION__;
default: throw __FUNCTION__;
}
if (ConditionPassed(cond))
{
const u32 shifted = Shift(CPU.read_gpr(m), shift_t, shift_n, true);
if (set_flags)
{
bool carry, overflow;
const u32 res = AddWithCarry(CPU.read_gpr(n), shifted, false, carry, overflow);
CPU.write_gpr(d, res);
CPU.APSR.N = res >> 31;
CPU.APSR.Z = res == 0;
CPU.APSR.C = carry;
CPU.APSR.V = overflow;
}
else
{
CPU.write_gpr(d, CPU.read_gpr(n) + shifted);
}
}
}
void ARMv7Interpreter::ADD_RSR(const u32 data, const ARMv7_encoding type)
@ -133,20 +237,122 @@ void ARMv7Interpreter::ADD_RSR(const u32 data, const ARMv7_encoding type)
void ARMv7Interpreter::ADD_SPI(const u32 data, const ARMv7_encoding type)
{
u32 cond = CPU.ITSTATE.advance();
u32 d = 13;
bool set_flags = false;
u32 imm32 = 0;
switch (type)
{
case T1:
{
d = (data & 0x700) >> 8;
imm32 = (data & 0xff) << 2;
break;
}
case T2:
{
imm32 = (data & 0x7f) << 2;
break;
}
case T3:
{
d = (data & 0xf00) >> 8;
set_flags = (data & 0x100000);
imm32 = ThumbExpandImm((data & 0x4000000) >> 15 | (data & 0x7000) >> 4 | (data & 0xff));
if (d == 15 && set_flags)
{
throw "CMN (immediate)";
}
break;
}
case T4:
{
d = (data & 0xf00) >> 8;
set_flags = false;
imm32 = (data & 0x4000000) >> 15 | (data & 0x7000) >> 4 | (data & 0xff);
break;
}
case A1: throw __FUNCTION__;
default: throw __FUNCTION__;
}
if (ConditionPassed(cond))
{
if (set_flags)
{
bool carry, overflow;
const u32 res = AddWithCarry(CPU.SP, imm32, false, carry, overflow);
CPU.write_gpr(d, res);
CPU.APSR.N = res >> 31;
CPU.APSR.Z = res == 0;
CPU.APSR.C = carry;
CPU.APSR.V = overflow;
}
else
{
CPU.write_gpr(d, CPU.SP + imm32);
}
}
}
void ARMv7Interpreter::ADD_SPR(const u32 data, const ARMv7_encoding type)
{
u32 cond = CPU.ITSTATE.advance();
u32 d = 13;
u32 m = 0;
bool set_flags = false;
auto shift_t = SRType_LSL;
u32 shift_n = 0;
switch (type)
{
case T1:
{
m = d = (data & 0x80) >> 4 | (data & 0x7);
break;
}
case T2:
{
m = (data & 0x78) >> 3;
if (m == 13)
{
throw "ADD_SPR_T2: T1";
}
break;
}
case T3:
{
d = (data & 0xf00) >> 8;
m = (data & 0xf);
set_flags = (data & 0x100000);
shift_t = DecodeImmShift((data & 0x30) >> 4, (data & 0x7000) >> 10 | (data & 0xc0) >> 6, &shift_n);
break;
}
case A1: throw __FUNCTION__;
default: throw __FUNCTION__;
}
if (ConditionPassed(cond))
{
const u32 shifted = Shift(CPU.read_gpr(m), shift_t, shift_n, CPU.APSR.C);
if (set_flags)
{
bool carry, overflow;
const u32 res = AddWithCarry(CPU.SP, shifted, false, carry, overflow);
CPU.write_gpr(d, res);
CPU.APSR.N = res >> 31;
CPU.APSR.Z = res == 0;
CPU.APSR.C = carry;
CPU.APSR.V = overflow;
}
else
{
CPU.write_gpr(d, CPU.SP + CPU.read_gpr(m));
}
}
}
@ -918,20 +1124,97 @@ void ARMv7Interpreter::LDRSH_REG(const u32 data, const ARMv7_encoding type)
void ARMv7Interpreter::LSL_IMM(const u32 data, const ARMv7_encoding type)
{
bool set_flags = !CPU.ITSTATE;
u32 cond = CPU.ITSTATE.advance();
u32 d = 0;
u32 m = 0;
u32 shift_n = 0;
switch (type)
{
case T1:
{
d = (data & 0x7);
m = (data & 0x38) >> 3;
shift_n = (data & 0x7c0) >> 6;
if (!shift_n)
{
throw "MOV (register)";
}
break;
}
case T2:
{
d = (data & 0xf00) >> 8;
m = (data & 0xf);
set_flags = (data & 0x100000);
shift_n = (data & 0x7000) >> 10 | (data & 0xc0) >> 6;
if (!shift_n)
{
throw "MOV (register)";
}
break;
}
case A1: throw __FUNCTION__;
default: throw __FUNCTION__;
}
if (ConditionPassed(cond))
{
bool carry;
const u32 res = Shift_C(CPU.read_gpr(m), SRType_LSL, shift_n, CPU.APSR.C, carry);
CPU.write_gpr(d, res);
if (set_flags)
{
CPU.APSR.N = res >> 31;
CPU.APSR.Z = res == 0;
CPU.APSR.C = carry;
}
}
}
void ARMv7Interpreter::LSL_REG(const u32 data, const ARMv7_encoding type)
{
bool set_flags = !CPU.ITSTATE;
u32 cond = CPU.ITSTATE.advance();
u32 d = 0;
u32 n = 0;
u32 m = 0;
switch (type)
{
case T1:
{
d = n = (data & 0x7);
m = (data & 0x38) >> 3;
break;
}
case T2:
{
d = (data & 0xf00) >> 8;
n = (data & 0xf0000) >> 16;
m = (data & 0xf);
set_flags = (data & 0x100000);
break;
}
case A1: throw __FUNCTION__;
default: throw __FUNCTION__;
}
if (ConditionPassed(cond))
{
bool carry;
const u32 res = Shift_C(CPU.read_gpr(n), SRType_LSL, (CPU.read_gpr(m) & 0xff), CPU.APSR.C, carry);
CPU.write_gpr(d, res);
if (set_flags)
{
CPU.APSR.N = res >> 31;
CPU.APSR.Z = res == 0;
CPU.APSR.C = carry;
}
}
}

@ -132,75 +132,72 @@ public:
return shift_t;
}
u32 LSL_C(u32 x, int shift, bool& carry_out)
u32 LSL_C(u32 x, s32 shift, bool& carry_out)
{
u32 extended_x = x << shift;
carry_out = (extended_x >> 31) ? 1 : 0;
return extended_x & ~(1 << 31);
assert(shift > 0);
carry_out = shift <= 32 ? x & (1 << (32 - shift)) : false;
return shift < 32 ? x << shift : 0;
}
u32 LSL(u32 x, int shift)
u32 LSL(u32 x, s32 shift)
{
if(!shift) return x;
bool carry_out;
return LSL_C(x, shift, carry_out);
assert(shift >= 0);
return shift < 32 ? x << shift : 0;
}
u32 LSR_C(u32 x, int shift, bool& carry_out)
u32 LSR_C(u32 x, s32 shift, bool& carry_out)
{
carry_out = (x >> (shift - 1)) & 0x1;
return x >> shift;
assert(shift > 0);
carry_out = shift <= 32 ? x & (1 << (shift - 1)) : false;
return shift < 32 ? x >> shift : 0;
}
u32 LSR(u32 x, int shift)
u32 LSR(u32 x, s32 shift)
{
if(!shift) return x;
bool carry_out;
return LSR_C(x, shift, carry_out);
assert(shift >= 0);
return shift < 32 ? x >> shift : 0;
}
s32 ASR_C(s32 x, int shift, bool& carry_out)
s32 ASR_C(s32 x, s32 shift, bool& carry_out)
{
carry_out = (x >> (shift - 1)) & 0x1;
return x >> shift;
assert(shift > 0);
carry_out = shift <= 32 ? x & (1 << (shift - 1)) : false;
return shift < 32 ? x >> shift : x >> 31;
}
s32 ASR(s32 x, int shift)
s32 ASR(s32 x, s32 shift)
{
if(!shift) return x;
bool carry_out;
return ASR_C(x, shift, carry_out);
assert(shift >= 0);
return shift < 32 ? x >> shift : x >> 31;
}
u32 ROR_C(u32 x, int shift, bool& carry_out)
u32 ROR_C(u32 x, s32 shift, bool& carry_out)
{
u32 result = LSR(x, shift) | LSL(x, 32 - shift);
carry_out = (result >> 30) & 0x1;
return result;
assert(shift);
carry_out = x & (1 << (shift - 1));
return x >> shift | x << (32 - shift);
}
s32 ROR(s32 x, int shift)
u32 ROR(u32 x, s32 shift)
{
if(!shift) return x;
bool carry_out;
return ROR_C(x, shift, carry_out);
return x >> shift | x << (32 - shift);
}
template<typename T> T RRX_C(T x, bool carry_in, bool& carry_out)
u32 RRX_C(u32 x, bool carry_in, bool& carry_out)
{
carry_out = x & 0x1;
return ((u32)carry_in << 31) | (x & 0x7ffffffe);
return ((u32)carry_in << 31) | (x >> 1);
}
s32 RRX(s32 x, int shift)
u32 RRX(u32 x, bool carry_in)
{
if(!shift) return x;
bool carry_out;
return RRX_C(x, shift, carry_out);
return ((u32)carry_in << 31) | (x >> 1);
}
template<typename T> T Shift_C(T value, SRType type, uint amount, bool carry_in, bool& carry_out)
template<typename T> T Shift_C(T value, SRType type, s32 amount, bool carry_in, bool& carry_out)
{
assert(type != SRType_RRX || amount == 1);
if(amount)
{
switch(type)
@ -209,7 +206,7 @@ public:
case SRType_LSR: return LSR_C(value, amount, carry_out);
case SRType_ASR: return ASR_C(value, amount, carry_out);
case SRType_ROR: return ROR_C(value, amount, carry_out);
case SRType_RRX: return RRX_C(value, amount, carry_out);
case SRType_RRX: return RRX_C(value, carry_in, carry_out);
}
}
@ -217,7 +214,7 @@ public:
return value;
}
template<typename T> T Shift(T value, SRType type, u32 amount, bool carry_in)
template<typename T> T Shift(T value, SRType type, s32 amount, bool carry_in)
{
bool carry_out;
return Shift_C(value, type, amount, carry_in, carry_out);

@ -350,6 +350,15 @@ static const ARMv7_opcode_t ARMv7_opcode_table[] =
ARMv7_OP4(0x0fe0, 0x0010, 0x00a0, 0x0000, A1, ADC_REG),
ARMv7_OP4(0x0fe0, 0x0090, 0x00a0, 0x0010, A1, ADC_RSR),
ARMv7_OP2(0xf800, 0xa800, T1, ADD_SPI),
ARMv7_OP2(0xff80, 0xb000, T2, ADD_SPI),
ARMv7_OP4(0xfbef, 0x8000, 0xf10d, 0x0000, T3, ADD_SPI),
ARMv7_OP4(0xfbff, 0x8000, 0xf20d, 0x0000, T4, ADD_SPI),
ARMv7_OP4(0x0fef, 0x0000, 0x028d, 0x0000, A1, ADD_SPI),
ARMv7_OP2(0xff78, 0x4468, T1, ADD_SPR),
ARMv7_OP2(0xff87, 0x4485, T2, ADD_SPR),
ARMv7_OP4(0xffef, 0x8000, 0xeb0d, 0x0000, T3, ADD_SPR),
ARMv7_OP4(0x0fef, 0x0010, 0x008d, 0x0000, A1, ADD_SPR),
ARMv7_OP2(0xfe00, 0x1c00, T1, ADD_IMM),
ARMv7_OP2(0xf800, 0x3000, T2, ADD_IMM),
ARMv7_OP4(0xfbe0, 0x8000, 0xf100, 0x0000, T3, ADD_IMM),
@ -360,15 +369,6 @@ static const ARMv7_opcode_t ARMv7_opcode_table[] =
ARMv7_OP4(0xffe0, 0x8000, 0xeb00, 0x0000, T3, ADD_REG),
ARMv7_OP4(0x0fe0, 0x0010, 0x0080, 0x0000, A1, ADD_REG),
ARMv7_OP4(0x0fe0, 0x0090, 0x0080, 0x0010, A1, ADD_RSR),
ARMv7_OP2(0xf800, 0xa800, T1, ADD_SPI),
ARMv7_OP2(0xff80, 0xb000, T2, ADD_SPI),
ARMv7_OP4(0xfbef, 0x8000, 0xf10d, 0x0000, T3, ADD_SPI),
ARMv7_OP4(0xfbff, 0x8000, 0xf20d, 0x0000, T4, ADD_SPI),
ARMv7_OP4(0x0fef, 0x0000, 0x028d, 0x0000, A1, ADD_SPI),
ARMv7_OP2(0xff78, 0x4468, T1, ADD_SPR),
ARMv7_OP2(0xff87, 0x4485, T2, ADD_SPR),
ARMv7_OP4(0xffef, 0x8000, 0xeb0d, 0x0000, T3, ADD_SPR),
ARMv7_OP4(0x0fef, 0x0010, 0x008d, 0x0000, A1, ADD_SPR),
ARMv7_OP2(0xf800, 0xa000, T1, ADR),
ARMv7_OP4(0xfbff, 0x8000, 0xf2af, 0x0000, T2, ADR),

@ -5,14 +5,83 @@
extern psv_log_base sceLibKernel;
#pragma pack(push, 4)
typedef s32(*SceKernelThreadEntry)(u32 argSize, vm::psv::ptr<void> pArgBlock);
union SceKernelSysClock
{
struct
{
u32 low;
u32 hi;
};
u64 quad;
};
struct SceKernelThreadOptParam
{
u32 size;
u32 attr;
};
struct SceKernelThreadInfo
{
u32 size;
s32 processId;
char name[32];
u32 attr;
u32 status;
SceKernelThreadEntry entry;
vm::psv::ptr<void> pStack;
u32 stackSize;
s32 initPriority;
s32 currentPriority;
s32 initCpuAffinityMask;
s32 currentCpuAffinityMask;
s32 currentCpuId;
s32 lastExecutedCpuId;
u32 waitType;
s32 waitId;
s32 exitStatus;
SceKernelSysClock runClocks;
u32 intrPreemptCount;
u32 threadPreemptCount;
u32 threadReleaseCount;
s32 changeCpuCount;
s32 fNotifyCallback;
s32 reserved;
};
struct SceKernelThreadRunStatus
{
u32 size;
struct
{
s32 processId;
s32 threadId;
s32 priority;
} cpuInfo[4];
};
struct SceKernelSystemInfo
{
u32 size;
u32 activeCpuMask;
struct
{
SceKernelSysClock idleClock;
u32 comesOutOfIdleCount;
u32 threadSwitchCount;
} cpuInfo[4];
};
#pragma pack(pop, 4)
s32 sceKernelCreateThread(
vm::psv::ptr<const char> pName,
vm::psv::ptr<SceKernelThreadEntry> entry,
@ -28,6 +97,167 @@ s32 sceKernelCreateThread(
return SCE_OK;
}
s32 sceKernelStartThread(s32 threadId, u32 argSize, vm::psv::ptr<const void> pArgBlock)
{
sceLibKernel.Todo("sceKernelStartThread(threadId=%d, argSize=%d, pArgBlock_addr=0x%x)", threadId, argSize, pArgBlock.addr());
return SCE_OK;
}
s32 sceKernelExitThread(s32 exitStatus)
{
sceLibKernel.Todo("sceKernelExitThread(exitStatus=0x%x)", exitStatus);
return SCE_OK;
}
s32 sceKernelDeleteThread(s32 threadId)
{
sceLibKernel.Todo("sceKernelDeleteThread(threadId=%d)", threadId);
return SCE_OK;
}
s32 sceKernelExitDeleteThread(s32 exitStatus)
{
sceLibKernel.Todo("sceKernelExitDeleteThread(exitStatus=0x%x)", exitStatus);
return SCE_OK;
}
s32 sceKernelChangeThreadCpuAffinityMask(s32 threadId, s32 cpuAffinityMask)
{
sceLibKernel.Todo("sceKernelChangeThreadCpuAffinityMask(threadId=%d, cpuAffinityMask=0x%x)", threadId, cpuAffinityMask);
return SCE_OK;
}
s32 sceKernelGetThreadCpuAffinityMask(s32 threadId)
{
sceLibKernel.Todo("sceKernelGetThreadCpuAffinityMask(threadId=0x%x)", threadId);
return SCE_OK;
}
s32 sceKernelChangeThreadPriority(s32 threadId, s32 priority)
{
sceLibKernel.Todo("sceKernelChangeThreadPriority(threadId=0x%x, priority=%d)", threadId, priority);
return SCE_OK;
}
s32 sceKernelGetThreadCurrentPriority()
{
sceLibKernel.Todo("sceKernelGetThreadCurrentPriority()");
return SCE_OK;
}
s32 sceKernelGetThreadId()
{
sceLibKernel.Todo("sceKernelGetThreadId()");
return SCE_OK;
}
s32 sceKernelChangeCurrentThreadAttr(u32 clearAttr, u32 setAttr)
{
sceLibKernel.Todo("sceKernelChangeCurrentThreadAttr()");
return SCE_OK;
}
s32 sceKernelGetThreadExitStatus(s32 threadId, vm::psv::ptr<s32> pExitStatus)
{
sceLibKernel.Todo("sceKernelGetThreadExitStatus(threadId=%d, pExitStatus_addr=0x%x)", threadId, pExitStatus.addr());
return SCE_OK;
}
s32 sceKernelGetProcessId()
{
sceLibKernel.Todo("sceKernelGetProcessId()");
return SCE_OK;
}
s32 sceKernelCheckWaitableStatus()
{
sceLibKernel.Todo("sceKernelCheckWaitableStatus()");
return SCE_OK;
}
s32 sceKernelGetThreadInfo(s32 threadId, vm::psv::ptr<SceKernelThreadInfo> pInfo)
{
sceLibKernel.Todo("sceKernelGetThreadInfo(threadId=%d, pInfo_addr=0x%x)", threadId, pInfo.addr());
return SCE_OK;
}
s32 sceKernelGetThreadRunStatus(vm::psv::ptr<SceKernelThreadRunStatus> pStatus)
{
sceLibKernel.Todo("sceKernelGetThreadRunStatus(pStatus_addr=0x%x)", pStatus.addr());
return SCE_OK;
}
s32 sceKernelGetSystemInfo(vm::psv::ptr<SceKernelSystemInfo> pInfo)
{
sceLibKernel.Todo("sceKernelGetSystemInfo(pInfo_addr=0x%x)", pInfo.addr());
return SCE_OK;
}
s32 sceKernelGetThreadmgrUIDClass(s32 uid)
{
sceLibKernel.Todo("sceKernelGetThreadmgrUIDClass(uid=%d)", uid);
return SCE_OK;
}
s32 sceKernelChangeThreadVfpException(s32 clearMask, s32 setMask)
{
sceLibKernel.Todo("sceKernelChangeThreadVfpException(clearMask=0x%x, setMask=0x%x)", clearMask, setMask);
return SCE_OK;
}
s32 sceKernelGetCurrentThreadVfpException()
{
sceLibKernel.Todo("sceKernelGetCurrentThreadVfpException()");
return SCE_OK;
}
s32 sceKernelDelayThread(u32 usec)
{
sceLibKernel.Todo("sceKernelDelayThread()");
return SCE_OK;
}
s32 sceKernelDelayThreadCB(u32 usec)
{
sceLibKernel.Todo("sceKernelDelayThreadCB()");
return SCE_OK;
}
s32 sceKernelWaitThreadEnd(s32 threadId, vm::psv::ptr<s32> pExitStatus, vm::psv::ptr<u32> pTimeout)
{
sceLibKernel.Todo("sceKernelWaitThreadEnd(threadId=%d, pExitStatus_addr=0x%x, pTimeout_addr=0x%x)", threadId, pExitStatus.addr(), pTimeout.addr());
return SCE_OK;
}
s32 sceKernelWaitThreadEndCB(s32 threadId, vm::psv::ptr<s32> pExitStatus, vm::psv::ptr<u32> pTimeout)
{
sceLibKernel.Todo("sceKernelWaitThreadEndCB(threadId=%d, pExitStatus_addr=0x%x, pTimeout_addr=0x%x)", threadId, pExitStatus.addr(), pTimeout.addr());
return SCE_OK;
}
#define REG_FUNC(nid, name) reg_psv_func(nid, &sceLibKernel, #name, &name)
psv_log_base sceLibKernel = []() -> psv_log_base
@ -145,8 +375,8 @@ psv_log_base sceLibKernel = []() -> psv_log_base
//REG_FUNC(0x4C7AD128, sceKernelPowerLock);
//REG_FUNC(0xAF8E9C11, sceKernelPowerUnlock);
//REG_FUNC(0xB295EB61, sceKernelGetTLSAddr);
//REG_FUNC(0xFB972F9, sceKernelGetThreadId);
//REG_FUNC(0xA37A6057, sceKernelGetCurrentThreadVfpException);
REG_FUNC(0xFB972F9, sceKernelGetThreadId);
REG_FUNC(0xA37A6057, sceKernelGetCurrentThreadVfpException);
//REG_FUNC(0xCA71EA2, sceKernelSendMsgPipe);
//REG_FUNC(0xA5CA74AC, sceKernelSendMsgPipeCB);
//REG_FUNC(0xDFC670E0, sceKernelTrySendMsgPipe);
@ -158,23 +388,23 @@ psv_log_base sceLibKernel = []() -> psv_log_base
//REG_FUNC(0x9EF798C1, sceKernelTryLockLwMutex);
//REG_FUNC(0x499EA781, sceKernelUnlockLwMutex);
//REG_FUNC(0xF7D8F1FC, sceKernelGetLwMutexInfo);
//REG_FUNC(0xDDB395A9, sceKernelWaitThreadEnd);
//REG_FUNC(0xC54941ED, sceKernelWaitThreadEndCB);
//REG_FUNC(0xD5DC26C4, sceKernelGetThreadExitStatus);
REG_FUNC(0xDDB395A9, sceKernelWaitThreadEnd);
REG_FUNC(0xC54941ED, sceKernelWaitThreadEndCB);
REG_FUNC(0xD5DC26C4, sceKernelGetThreadExitStatus);
//REG_FUNC(0x4373B548, __sce_aeabi_idiv0);
//REG_FUNC(0xFB235848, __sce_aeabi_ldiv0);
//REG_FUNC(0xF08DE149, sceKernelStartThread);
//REG_FUNC(0x58DDAC4F, sceKernelDeleteThread);
//REG_FUNC(0x5150577B, sceKernelChangeThreadCpuAffinityMask);
//REG_FUNC(0x8C57AC2A, sceKernelGetThreadCpuAffinityMask);
//REG_FUNC(0xDF7E6EDA, sceKernelChangeThreadPriority);
REG_FUNC(0xF08DE149, sceKernelStartThread);
REG_FUNC(0x58DDAC4F, sceKernelDeleteThread);
REG_FUNC(0x5150577B, sceKernelChangeThreadCpuAffinityMask);
REG_FUNC(0x8C57AC2A, sceKernelGetThreadCpuAffinityMask);
REG_FUNC(0xDF7E6EDA, sceKernelChangeThreadPriority);
//REG_FUNC(0xBCB63B66, sceKernelGetThreadStackFreeSize);
//REG_FUNC(0x8D9C5461, sceKernelGetThreadInfo);
//REG_FUNC(0xD6B01013, sceKernelGetThreadRunStatus);
//REG_FUNC(0xE0241FAA, sceKernelGetSystemInfo);
//REG_FUNC(0xF994FE65, sceKernelGetThreadmgrUIDClass);
REG_FUNC(0x8D9C5461, sceKernelGetThreadInfo);
REG_FUNC(0xD6B01013, sceKernelGetThreadRunStatus);
REG_FUNC(0xE0241FAA, sceKernelGetSystemInfo);
REG_FUNC(0xF994FE65, sceKernelGetThreadmgrUIDClass);
//REG_FUNC(0xB4DE10C7, sceKernelGetActiveCpuMask);
//REG_FUNC(0x2C1321A3, sceKernelChangeThreadVfpException);
REG_FUNC(0x2C1321A3, sceKernelChangeThreadVfpException);
//REG_FUNC(0x3849359A, sceKernelCreateCallback);
//REG_FUNC(0x88DD1BC8, sceKernelGetCallbackInfo);
//REG_FUNC(0x464559D3, sceKernelDeleteCallback);
@ -380,15 +610,15 @@ psv_log_base sceLibKernel = []() -> psv_log_base
//REG_FUNC(0x800EDCC1, sceKernelClearDipsw);
/* SceThreadmgr */
//REG_FUNC(0xC8A38E1, sceKernelExitThread);
//REG_FUNC(0x1D17DECF, sceKernelExitDeleteThread);
//REG_FUNC(0x4B675D05, sceKernelDelayThread);
//REG_FUNC(0x9C0180E1, sceKernelDelayThreadCB);
REG_FUNC(0xC8A38E1, sceKernelExitThread);
REG_FUNC(0x1D17DECF, sceKernelExitDeleteThread);
REG_FUNC(0x4B675D05, sceKernelDelayThread);
REG_FUNC(0x9C0180E1, sceKernelDelayThreadCB);
//REG_FUNC(0x1173F8, sceKernelChangeActiveCpuMask);
//REG_FUNC(0x1414F0B, sceKernelGetThreadCurrentPriority);
//REG_FUNC(0x751C9B7A, sceKernelChangeCurrentThreadAttr);
//REG_FUNC(0xD9BD74EB, sceKernelCheckWaitableStatus);
//REG_FUNC(0x9DCB4B7A, sceKernelGetProcessId);
REG_FUNC(0x1414F0B, sceKernelGetThreadCurrentPriority);
REG_FUNC(0x751C9B7A, sceKernelChangeCurrentThreadAttr);
REG_FUNC(0xD9BD74EB, sceKernelCheckWaitableStatus);
REG_FUNC(0x9DCB4B7A, sceKernelGetProcessId);
//REG_FUNC(0xE53E41F6, sceKernelCheckCallback);
//REG_FUNC(0xF4EE4FA9, sceKernelGetSystemTimeWide);
//REG_FUNC(0x47F6DE49, sceKernelGetSystemTimeLow);

@ -44,9 +44,11 @@ namespace sce_libc_func
::memcpy(dst.get_ptr(), src.get_ptr(), size);
}
void _Assert()
void _Assert(vm::psv::ptr<const char> text, vm::psv::ptr<const char> func)
{
sceLibc.Todo(__FUNCTION__);
sceLibc.Error("_Assert(text_addr=0x%x, func_addr=0x%x)", text.addr(), func.addr());
LOG_ERROR(TTY, "%s : %s", func.get_ptr(), text.get_ptr());
Emu.Pause();
}
}