mirror of
https://github.com/RPCS3/rpcs3.git
synced 2025-03-14 01:27:00 +00:00
rsx_method_t extended
rsx_methods.cpp cleanup
This commit is contained in:
parent
6a9f3040e1
commit
1c69eb2b73
@ -478,7 +478,7 @@ namespace rsx
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if (auto method = methods[reg])
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{
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method(this, value);
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method(this, reg, value);
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}
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}
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@ -26,7 +26,7 @@ cfg::map_entry<double> g_cfg_rsx_frame_limit(cfg::root.video, "Frame limit",
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namespace rsx
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{
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rsx_state method_registers;
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using rsx_method_t = void(*)(class thread*, u32);
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std::array<rsx_method_t, 0x10000 / 4> methods{};
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template<typename Type> struct vertex_data_type_from_element_type;
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@ -37,12 +37,12 @@ namespace rsx
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namespace nv406e
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{
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force_inline void set_reference(thread* rsx, u32 arg)
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void set_reference(thread* rsx, u32 _reg, u32 arg)
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{
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rsx->ctrl->ref.exchange(arg);
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}
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force_inline void semaphore_acquire(thread* rsx, u32 arg)
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void semaphore_acquire(thread* rsx, u32 _reg, u32 arg)
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{
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//TODO: dma
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while (vm::ps3::read32(rsx->label_addr + method_registers.semaphore_offset_406e()) != arg)
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@ -54,7 +54,7 @@ namespace rsx
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}
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}
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force_inline void semaphore_release(thread* rsx, u32 arg)
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void semaphore_release(thread* rsx, u32 _reg, u32 arg)
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{
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//TODO: dma
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vm::ps3::write32(rsx->label_addr + method_registers.semaphore_offset_406e(), arg);
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@ -63,21 +63,45 @@ namespace rsx
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namespace nv4097
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{
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force_inline void texture_read_semaphore_release(thread* rsx, u32 arg)
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void clear(thread* rsx, u32 _reg, u32 arg)
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{
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// TODO: every backend must override method table to insert its own handlers
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if (!rsx->do_method(/* reg << 2 */ NV4097_CLEAR_SURFACE, arg))
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{
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//
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}
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if (rsx->capture_current_frame)
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{
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rsx->capture_frame("clear");
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}
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}
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void texture_read_semaphore_release(thread* rsx, u32 _reg, u32 arg)
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{
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if (!rsx->do_method(/* reg << 2 */ NV4097_TEXTURE_READ_SEMAPHORE_RELEASE, arg))
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{
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//
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}
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//TODO: dma
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vm::ps3::write32(rsx->label_addr + method_registers.semaphore_offset_4097(), arg);
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}
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force_inline void back_end_write_semaphore_release(thread* rsx, u32 arg)
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void back_end_write_semaphore_release(thread* rsx, u32 _reg, u32 arg)
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{
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if (!rsx->do_method(/* reg << 2 */ NV4097_BACK_END_WRITE_SEMAPHORE_RELEASE, arg))
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{
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//
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}
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//TODO: dma
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vm::ps3::write32(rsx->label_addr + method_registers.semaphore_offset_4097(),
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(arg & 0xff00ff00) | ((arg & 0xff) << 16) | ((arg >> 16) & 0xff));
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}
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template<u32 id, u32 index, int count, typename type>
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force_inline void set_vertex_data_impl(thread* rsx, u32 arg)
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void set_vertex_data_impl(thread* rsx, u32 arg)
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{
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static const size_t increment_per_array_index = (count * sizeof(type)) / sizeof(u32);
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@ -96,7 +120,7 @@ namespace rsx
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template<u32 index>
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struct set_vertex_data4ub_m
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{
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force_inline static void impl(thread* rsx, u32 arg)
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static void impl(thread* rsx, u32 _reg, u32 arg)
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{
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set_vertex_data_impl<NV4097_SET_VERTEX_DATA4UB_M, index, 4, u8>(rsx, arg);
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}
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@ -105,7 +129,7 @@ namespace rsx
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template<u32 index>
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struct set_vertex_data1f_m
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{
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force_inline static void impl(thread* rsx, u32 arg)
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static void impl(thread* rsx, u32 _reg, u32 arg)
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{
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set_vertex_data_impl<NV4097_SET_VERTEX_DATA1F_M, index, 1, f32>(rsx, arg);
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}
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@ -114,7 +138,7 @@ namespace rsx
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template<u32 index>
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struct set_vertex_data2f_m
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{
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force_inline static void impl(thread* rsx, u32 arg)
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static void impl(thread* rsx, u32 _reg, u32 arg)
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{
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set_vertex_data_impl<NV4097_SET_VERTEX_DATA2F_M, index, 2, f32>(rsx, arg);
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}
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@ -123,7 +147,7 @@ namespace rsx
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template<u32 index>
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struct set_vertex_data3f_m
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{
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force_inline static void impl(thread* rsx, u32 arg)
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static void impl(thread* rsx, u32 _reg, u32 arg)
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{
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set_vertex_data_impl<NV4097_SET_VERTEX_DATA3F_M, index, 3, f32>(rsx, arg);
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}
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@ -132,7 +156,7 @@ namespace rsx
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template<u32 index>
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struct set_vertex_data4f_m
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{
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force_inline static void impl(thread* rsx, u32 arg)
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static void impl(thread* rsx, u32 _reg, u32 arg)
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{
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set_vertex_data_impl<NV4097_SET_VERTEX_DATA4F_M, index, 4, f32>(rsx, arg);
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}
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@ -141,7 +165,7 @@ namespace rsx
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template<u32 index>
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struct set_vertex_data2s_m
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{
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force_inline static void impl(thread* rsx, u32 arg)
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static void impl(thread* rsx, u32 _reg, u32 arg)
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{
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set_vertex_data_impl<NV4097_SET_VERTEX_DATA2S_M, index, 2, u16>(rsx, arg);
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}
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@ -150,7 +174,7 @@ namespace rsx
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template<u32 index>
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struct set_vertex_data4s_m
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{
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force_inline static void impl(thread* rsx, u32 arg)
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static void impl(thread* rsx, u32 _reg, u32 arg)
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{
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set_vertex_data_impl<NV4097_SET_VERTEX_DATA4S_M, index, 4, u16>(rsx, arg);
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}
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@ -159,7 +183,7 @@ namespace rsx
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template<u32 index>
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struct set_vertex_data_array_format
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{
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force_inline static void impl(thread* rsx, u32 arg)
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static void impl(thread* rsx, u32 _reg, u32 arg)
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{
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const typename rsx::registers_decoder<NV4097_SET_VERTEX_DATA_ARRAY_FORMAT + index>::decoded_type decoded_value(arg);
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rsx::method_registers.vertex_arrays_info[index].frequency = decoded_value.frequency();
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@ -169,7 +193,7 @@ namespace rsx
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}
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};
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force_inline void draw_arrays(thread* rsx, u32 arg)
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void draw_arrays(thread* rsx, u32 _reg, u32 arg)
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{
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rsx->draw_command = rsx::draw_command::array;
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u32 first = arg & 0xffffff;
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@ -178,7 +202,7 @@ namespace rsx
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rsx->first_count_commands.emplace_back(std::make_pair(first, count));
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}
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force_inline void draw_index_array(thread* rsx, u32 arg)
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void draw_index_array(thread* rsx, u32 _reg, u32 arg)
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{
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rsx->draw_command = rsx::draw_command::indexed;
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u32 first = arg & 0xffffff;
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@ -187,7 +211,7 @@ namespace rsx
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rsx->first_count_commands.emplace_back(std::make_pair(first, count));
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}
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force_inline void draw_inline_array(thread* rsx, u32 arg)
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void draw_inline_array(thread* rsx, u32 _reg, u32 arg)
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{
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rsx->draw_command = rsx::draw_command::inlined_array;
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rsx->draw_inline_vertex_array = true;
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@ -197,7 +221,7 @@ namespace rsx
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template<u32 index>
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struct set_transform_constant
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{
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force_inline static void impl(thread* rsxthr, u32 arg)
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static void impl(thread* rsxthr, u32 _reg, u32 arg)
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{
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static constexpr u32 reg = index / 4;
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static constexpr u8 subreg = index % 4;
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@ -211,13 +235,13 @@ namespace rsx
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template<u32 index>
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struct set_transform_program
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{
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force_inline static void impl(thread* rsx, u32 arg)
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static void impl(thread* rsx, u32 _reg, u32 arg)
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{
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method_registers.commit_4_transform_program_instructions(index);
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}
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};
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force_inline void set_begin_end(thread* rsxthr, u32 arg)
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void set_begin_end(thread* rsxthr, u32 _reg, u32 arg)
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{
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if (arg)
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{
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@ -257,7 +281,7 @@ namespace rsx
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}
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}
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force_inline void get_report(thread* rsx, u32 arg)
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void get_report(thread* rsx, u32 _reg, u32 arg)
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{
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u8 type = arg >> 24;
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u32 offset = arg & 0xffffff;
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@ -297,7 +321,7 @@ namespace rsx
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//result->padding = 0;
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}
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force_inline void clear_report_value(thread* rsx, u32 arg)
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void clear_report_value(thread* rsx, u32 _reg, u32 arg)
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{
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switch (arg)
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{
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@ -313,7 +337,7 @@ namespace rsx
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}
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}
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force_inline void set_surface_dirty_bit(thread* rsx, u32)
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void set_surface_dirty_bit(thread* rsx, u32 _reg, u32)
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{
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rsx->m_rtts_dirty = true;
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}
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@ -321,7 +345,7 @@ namespace rsx
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template<u32 index>
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struct set_texture_dirty_bit
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{
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force_inline static void impl(thread* rsx, u32 arg)
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static void impl(thread* rsx, u32 _reg, u32 arg)
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{
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rsx->m_textures_dirty[index] = true;
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}
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@ -333,7 +357,7 @@ namespace rsx
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template<u32 index>
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struct color
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{
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force_inline static void impl(u32 arg)
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static void impl(thread* rsx, u32 _reg, u32 arg)
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{
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u16 x = method_registers.nv308a_x();
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u16 y = method_registers.nv308a_y();
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@ -351,7 +375,7 @@ namespace rsx
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namespace nv3089
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{
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never_inline void image_in(thread *rsx, u32 arg)
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void image_in(thread *rsx, u32 _reg, u32 arg)
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{
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rsx::blit_engine::transfer_operation operation = method_registers.blit_engine_operation();
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@ -659,7 +683,7 @@ namespace rsx
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namespace nv0039
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{
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never_inline void buffer_notify(u32 arg)
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void buffer_notify(thread*, u32, u32 arg)
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{
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s32 in_pitch = method_registers.nv0039_input_pitch();
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s32 out_pitch = method_registers.nv0039_output_pitch();
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@ -713,7 +737,7 @@ namespace rsx
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}
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}
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void flip_command(thread* rsx, u32 arg)
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void flip_command(thread* rsx, u32, u32 arg)
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{
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if (user_asked_for_frame_capture)
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{
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@ -764,7 +788,7 @@ namespace rsx
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}
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}
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void user_command(thread* rsx, u32 arg)
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void user_command(thread* rsx, u32, u32 arg)
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{
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if (rsx->user_handler)
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{
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@ -856,172 +880,117 @@ namespace rsx
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registers[reg] = value;
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}
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struct __rsx_methods_t
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namespace method_detail
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{
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using rsx_impl_method_t = void(*)(u32);
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template<rsx_method_t impl_func>
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force_inline static void call_impl_func(thread *rsx, u32 arg)
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{
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impl_func(rsx, arg);
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}
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template<rsx_impl_method_t impl_func>
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force_inline static void call_impl_func(thread *rsx, u32 arg)
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{
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impl_func(arg);
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}
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template<int id, typename T, T impl_func>
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static void wrapper(thread *rsx, u32 arg)
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{
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// try process using gpu
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if (rsx->do_method(id, arg))
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{
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if (rsx->capture_current_frame && id == NV4097_CLEAR_SURFACE)
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rsx->capture_frame("clear");
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return;
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}
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// not handled by renderer
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// try process using cpu
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if (impl_func != nullptr)
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call_impl_func<impl_func>(rsx, arg);
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}
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template<int id, int step, int count, template<u32> class T, int index = 0>
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template<int Id, int Step, int Count, template<u32> class T, int Index = 0>
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struct bind_range_impl_t
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{
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force_inline static void impl()
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static inline void impl()
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{
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bind_range_impl_t<id + step, step, count, T, index + 1>::impl();
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bind<id, T<index>::impl>();
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methods[Id] = &T<Index>::impl;
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bind_range_impl_t<Id + Step, Step, Count, T, Index + 1>::impl();
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}
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};
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template<int id, int step, int count, template<u32> class T>
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struct bind_range_impl_t<id, step, count, T, count>
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template<int Id, int Step, int Count, template<u32> class T>
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struct bind_range_impl_t<Id, Step, Count, T, Count>
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{
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force_inline static void impl()
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static inline void impl()
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{
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}
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};
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template<int id, int step, int count, template<u32> class T, int index = 0>
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force_inline static void bind_range()
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template<int Id, int Step, int Count, template<u32> class T, int Index = 0>
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static inline void bind_range()
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{
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bind_range_impl_t<id, step, count, T, index>::impl();
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bind_range_impl_t<Id, Step, Count, T, Index>::impl();
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}
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[[noreturn]] never_inline static void bind_redefinition_error(int id)
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template<int Id, rsx_method_t Func>
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static void bind()
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{
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throw EXCEPTION("RSX method implementation redefinition (0x%04x)", id);
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methods[Id] = Func;
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}
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}
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template<int id, typename T, T impl_func>
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static void bind_impl()
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{
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if (methods[id])
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{
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bind_redefinition_error(id);
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}
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// TODO: implement this as virtual function: rsx::thread::init_methods() or something
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static const bool s_methods_init = []() -> bool
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{
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using namespace method_detail;
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methods[id] = wrapper<id, T, impl_func>;
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}
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// NV406E
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bind<NV406E_SET_REFERENCE, nv406e::set_reference>();
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bind<NV406E_SEMAPHORE_ACQUIRE, nv406e::semaphore_acquire>();
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bind<NV406E_SEMAPHORE_RELEASE, nv406e::semaphore_release>();
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template<int id, typename T, T impl_func>
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static void bind_cpu_only_impl()
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{
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if (methods[id])
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{
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bind_redefinition_error(id);
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}
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/*
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methods[id] = call_impl_func<impl_func>;
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}
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// Store previous fbo addresses to detect RTT config changes.
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std::array<u32, 4> m_previous_color_address = {};
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u32 m_previous_address_z = 0;
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u32 m_previous_target = 0;
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u32 m_previous_clip_horizontal = 0;
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u32 m_previous_clip_vertical = 0;
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*/
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template<int id, rsx_impl_method_t impl_func> static void bind() { bind_impl<id, rsx_impl_method_t, impl_func>(); }
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template<int id, rsx_method_t impl_func = nullptr> static void bind() { bind_impl<id, rsx_method_t, impl_func>(); }
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// NV4097
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bind<NV4097_TEXTURE_READ_SEMAPHORE_RELEASE, nv4097::texture_read_semaphore_release>();
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bind<NV4097_BACK_END_WRITE_SEMAPHORE_RELEASE, nv4097::back_end_write_semaphore_release>();
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bind<NV4097_SET_BEGIN_END, nv4097::set_begin_end>();
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bind<NV4097_CLEAR_SURFACE, nv4097::clear>();
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bind<NV4097_DRAW_ARRAYS, nv4097::draw_arrays>();
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bind<NV4097_DRAW_INDEX_ARRAY, nv4097::draw_index_array>();
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bind<NV4097_INLINE_ARRAY, nv4097::draw_inline_array>();
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bind_range<NV4097_SET_VERTEX_DATA_ARRAY_FORMAT, 1, 16, nv4097::set_vertex_data_array_format>();
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bind_range<NV4097_SET_VERTEX_DATA4UB_M, 1, 16, nv4097::set_vertex_data4ub_m>();
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bind_range<NV4097_SET_VERTEX_DATA1F_M, 1, 16, nv4097::set_vertex_data1f_m>();
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bind_range<NV4097_SET_VERTEX_DATA2F_M, 1, 32, nv4097::set_vertex_data2f_m>();
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bind_range<NV4097_SET_VERTEX_DATA3F_M, 1, 48, nv4097::set_vertex_data3f_m>();
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bind_range<NV4097_SET_VERTEX_DATA4F_M, 1, 64, nv4097::set_vertex_data4f_m>();
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||||
bind_range<NV4097_SET_VERTEX_DATA2S_M, 1, 16, nv4097::set_vertex_data2s_m>();
|
||||
bind_range<NV4097_SET_VERTEX_DATA4S_M, 1, 32, nv4097::set_vertex_data4s_m>();
|
||||
bind_range<NV4097_SET_TRANSFORM_CONSTANT, 1, 32, nv4097::set_transform_constant>();
|
||||
bind_range<NV4097_SET_TRANSFORM_PROGRAM + 3, 4, 128, nv4097::set_transform_program>();
|
||||
bind<NV4097_GET_REPORT, nv4097::get_report>();
|
||||
bind<NV4097_CLEAR_REPORT_VALUE, nv4097::clear_report_value>();
|
||||
bind<NV4097_SET_SURFACE_CLIP_HORIZONTAL, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_SURFACE_CLIP_VERTICAL, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_SURFACE_COLOR_AOFFSET, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_SURFACE_COLOR_BOFFSET, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_SURFACE_COLOR_COFFSET, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_SURFACE_COLOR_DOFFSET, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_SURFACE_ZETA_OFFSET, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_CONTEXT_DMA_COLOR_A, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_CONTEXT_DMA_COLOR_B, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_CONTEXT_DMA_COLOR_C, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_CONTEXT_DMA_COLOR_D, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_CONTEXT_DMA_ZETA, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_SURFACE_FORMAT, nv4097::set_surface_dirty_bit>();
|
||||
bind_range<NV4097_SET_TEXTURE_OFFSET, 8, 16, nv4097::set_texture_dirty_bit>();
|
||||
bind_range<NV4097_SET_TEXTURE_FORMAT, 8, 16, nv4097::set_texture_dirty_bit>();
|
||||
bind_range<NV4097_SET_TEXTURE_ADDRESS, 8, 16, nv4097::set_texture_dirty_bit>();
|
||||
bind_range<NV4097_SET_TEXTURE_CONTROL0, 8, 16, nv4097::set_texture_dirty_bit>();
|
||||
bind_range<NV4097_SET_TEXTURE_CONTROL1, 8, 16, nv4097::set_texture_dirty_bit>();
|
||||
bind_range<NV4097_SET_TEXTURE_CONTROL2, 8, 16, nv4097::set_texture_dirty_bit>();
|
||||
bind_range<NV4097_SET_TEXTURE_CONTROL3, 1, 16, nv4097::set_texture_dirty_bit>();
|
||||
bind_range<NV4097_SET_TEXTURE_FILTER, 8, 16, nv4097::set_texture_dirty_bit>();
|
||||
bind_range<NV4097_SET_TEXTURE_IMAGE_RECT, 8, 16, nv4097::set_texture_dirty_bit>();
|
||||
bind_range<NV4097_SET_TEXTURE_BORDER_COLOR, 8, 16, nv4097::set_texture_dirty_bit>();
|
||||
|
||||
//do not try process on gpu
|
||||
template<int id, rsx_impl_method_t impl_func> static void bind_cpu_only() { bind_cpu_only_impl<id, rsx_impl_method_t, impl_func>(); }
|
||||
//do not try process on gpu
|
||||
template<int id, rsx_method_t impl_func = nullptr> static void bind_cpu_only() { bind_cpu_only_impl<id, rsx_method_t, impl_func>(); }
|
||||
//NV308A
|
||||
bind_range<NV308A_COLOR, 1, 256, nv308a::color>();
|
||||
bind_range<NV308A_COLOR + 256, 1, 512, nv308a::color, 256>();
|
||||
|
||||
__rsx_methods_t()
|
||||
{
|
||||
// NV406E
|
||||
bind_cpu_only<NV406E_SET_REFERENCE, nv406e::set_reference>();
|
||||
bind<NV406E_SEMAPHORE_ACQUIRE, nv406e::semaphore_acquire>();
|
||||
bind<NV406E_SEMAPHORE_RELEASE, nv406e::semaphore_release>();
|
||||
//NV3089
|
||||
bind<NV3089_IMAGE_IN, nv3089::image_in>();
|
||||
|
||||
/*
|
||||
//NV0039
|
||||
bind<NV0039_BUFFER_NOTIFY, nv0039::buffer_notify>();
|
||||
|
||||
// Store previous fbo addresses to detect RTT config changes.
|
||||
std::array<u32, 4> m_previous_color_address = {};
|
||||
u32 m_previous_address_z = 0;
|
||||
u32 m_previous_target = 0;
|
||||
u32 m_previous_clip_horizontal = 0;
|
||||
u32 m_previous_clip_vertical = 0;
|
||||
*/
|
||||
// custom methods
|
||||
bind<GCM_FLIP_COMMAND, flip_command>();
|
||||
bind<GCM_SET_USER_COMMAND, user_command>();
|
||||
|
||||
// NV4097
|
||||
bind<NV4097_TEXTURE_READ_SEMAPHORE_RELEASE, nv4097::texture_read_semaphore_release>();
|
||||
bind<NV4097_BACK_END_WRITE_SEMAPHORE_RELEASE, nv4097::back_end_write_semaphore_release>();
|
||||
bind<NV4097_SET_BEGIN_END, nv4097::set_begin_end>();
|
||||
bind<NV4097_CLEAR_SURFACE>();
|
||||
bind<NV4097_DRAW_ARRAYS, nv4097::draw_arrays>();
|
||||
bind<NV4097_DRAW_INDEX_ARRAY, nv4097::draw_index_array>();
|
||||
bind<NV4097_INLINE_ARRAY, nv4097::draw_inline_array>();
|
||||
bind_range<NV4097_SET_VERTEX_DATA_ARRAY_FORMAT, 1, 16, nv4097::set_vertex_data_array_format>();
|
||||
bind_range<NV4097_SET_VERTEX_DATA4UB_M, 1, 16, nv4097::set_vertex_data4ub_m>();
|
||||
bind_range<NV4097_SET_VERTEX_DATA1F_M, 1, 16, nv4097::set_vertex_data1f_m>();
|
||||
bind_range<NV4097_SET_VERTEX_DATA2F_M, 1, 32, nv4097::set_vertex_data2f_m>();
|
||||
bind_range<NV4097_SET_VERTEX_DATA3F_M, 1, 48, nv4097::set_vertex_data3f_m>();
|
||||
bind_range<NV4097_SET_VERTEX_DATA4F_M, 1, 64, nv4097::set_vertex_data4f_m>();
|
||||
bind_range<NV4097_SET_VERTEX_DATA2S_M, 1, 16, nv4097::set_vertex_data2s_m>();
|
||||
bind_range<NV4097_SET_VERTEX_DATA4S_M, 1, 32, nv4097::set_vertex_data4s_m>();
|
||||
bind_range<NV4097_SET_TRANSFORM_CONSTANT, 1, 32, nv4097::set_transform_constant>();
|
||||
bind_range<NV4097_SET_TRANSFORM_PROGRAM + 3, 4, 128, nv4097::set_transform_program>();
|
||||
bind_cpu_only<NV4097_GET_REPORT, nv4097::get_report>();
|
||||
bind_cpu_only<NV4097_CLEAR_REPORT_VALUE, nv4097::clear_report_value>();
|
||||
bind<NV4097_SET_SURFACE_CLIP_HORIZONTAL, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_SURFACE_CLIP_VERTICAL, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_SURFACE_COLOR_AOFFSET, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_SURFACE_COLOR_BOFFSET, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_SURFACE_COLOR_COFFSET, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_SURFACE_COLOR_DOFFSET, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_SURFACE_ZETA_OFFSET, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_CONTEXT_DMA_COLOR_A, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_CONTEXT_DMA_COLOR_B, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_CONTEXT_DMA_COLOR_C, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_CONTEXT_DMA_COLOR_D, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_CONTEXT_DMA_ZETA, nv4097::set_surface_dirty_bit>();
|
||||
bind<NV4097_SET_SURFACE_FORMAT, nv4097::set_surface_dirty_bit>();
|
||||
bind_range<NV4097_SET_TEXTURE_OFFSET, 8, 16, nv4097::set_texture_dirty_bit>();
|
||||
bind_range<NV4097_SET_TEXTURE_FORMAT, 8, 16, nv4097::set_texture_dirty_bit>();
|
||||
bind_range<NV4097_SET_TEXTURE_ADDRESS, 8, 16, nv4097::set_texture_dirty_bit>();
|
||||
bind_range<NV4097_SET_TEXTURE_CONTROL0, 8, 16, nv4097::set_texture_dirty_bit>();
|
||||
bind_range<NV4097_SET_TEXTURE_CONTROL1, 8, 16, nv4097::set_texture_dirty_bit>();
|
||||
bind_range<NV4097_SET_TEXTURE_CONTROL2, 8, 16, nv4097::set_texture_dirty_bit>();
|
||||
bind_range<NV4097_SET_TEXTURE_CONTROL3, 1, 16, nv4097::set_texture_dirty_bit>();
|
||||
bind_range<NV4097_SET_TEXTURE_FILTER, 8, 16, nv4097::set_texture_dirty_bit>();
|
||||
bind_range<NV4097_SET_TEXTURE_IMAGE_RECT, 8, 16, nv4097::set_texture_dirty_bit>();
|
||||
bind_range<NV4097_SET_TEXTURE_BORDER_COLOR, 8, 16, nv4097::set_texture_dirty_bit>();
|
||||
|
||||
//NV308A
|
||||
bind_range<NV308A_COLOR, 1, 256, nv308a::color>();
|
||||
bind_range<NV308A_COLOR + 256, 1, 512, nv308a::color, 256>();
|
||||
|
||||
//NV3089
|
||||
bind<NV3089_IMAGE_IN, nv3089::image_in>();
|
||||
|
||||
//NV0039
|
||||
bind<NV0039_BUFFER_NOTIFY, nv0039::buffer_notify>();
|
||||
|
||||
// custom methods
|
||||
bind_cpu_only<GCM_FLIP_COMMAND, flip_command>();
|
||||
bind_cpu_only<GCM_SET_USER_COMMAND, user_command>();
|
||||
}
|
||||
} __rsx_methods;
|
||||
return true;
|
||||
}();
|
||||
}
|
||||
|
@ -14,6 +14,8 @@
|
||||
|
||||
namespace rsx
|
||||
{
|
||||
using rsx_method_t = void(*)(class thread*, u32 reg, u32 arg);
|
||||
|
||||
//TODO
|
||||
union alignas(4) method_registers_t
|
||||
{
|
||||
@ -1114,7 +1116,6 @@ namespace rsx
|
||||
}
|
||||
};
|
||||
|
||||
using rsx_method_t = void(*)(class thread*, u32);
|
||||
extern rsx_state method_registers;
|
||||
extern std::array<rsx_method_t, 0x10000 / 4> methods;
|
||||
}
|
||||
|
Loading…
x
Reference in New Issue
Block a user