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spu: improve dfnma instruction

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scribam 2018-06-28 13:59:27 +02:00 committed by Ivan
parent 2ed6e51d24
commit 1b0f5b1ed9
3 changed files with 4 additions and 5 deletions
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5
rpcs3/Emu/Cell/SPUASMJITRecompiler.cpp
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@ -3921,9 +3921,8 @@ void spu_recompiler::DFNMA(spu_opcode_t op)
const XmmLink& va = XmmGet(op.ra, XmmType::Double);
const XmmLink& vt = XmmGet(op.rt, XmmType::Double);
c->mulpd(va, SPU_OFF_128(gpr, op.rb));
c->addpd(vt, va);
c->xorpd(va, va);
c->subpd(va, vt);
c->addpd(va, vt);
c->xorpd(va, XmmConst(_mm_set1_epi64x(0x8000000000000000)));
c->movapd(SPU_OFF_128(gpr, op.rt), va);
}

2
rpcs3/Emu/Cell/SPUInterpreter.cpp
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@ -1090,7 +1090,7 @@ bool spu_interpreter_fast::DFNMS(SPUThread& spu, spu_opcode_t op)
bool spu_interpreter_fast::DFNMA(SPUThread& spu, spu_opcode_t op)
{
spu.gpr[op.rt].vd = _mm_sub_pd(_mm_set1_pd(0.0), _mm_add_pd(_mm_mul_pd(spu.gpr[op.ra].vd, spu.gpr[op.rb].vd), spu.gpr[op.rt].vd));
spu.gpr[op.rt].vd = _mm_xor_pd(_mm_add_pd(_mm_mul_pd(spu.gpr[op.ra].vd, spu.gpr[op.rb].vd), spu.gpr[op.rt].vd), _mm_set1_pd(-0.0));
return true;
}

2
rpcs3/Emu/Cell/SPURecompiler.cpp
View File

@ -4141,7 +4141,7 @@ public:
void DFNMA(spu_opcode_t op) //
{
set_vr(op.rt, -get_vr<f64[2]>(op.rt) - get_vr<f64[2]>(op.ra) * get_vr<f64[2]>(op.rb));
set_vr(op.rt, -(get_vr<f64[2]>(op.ra) * get_vr<f64[2]>(op.rb) + get_vr<f64[2]>(op.rt)));
}
void FREST(spu_opcode_t op) //