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ARMv7: LDRB_IMM, STRB_IMM
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parent
912e3fc213
commit
14efde9190
rpcs3/Emu/ARMv7
@ -44,20 +44,20 @@ const ARMv7_opcode_t ARMv7_opcode_table[] =
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ARMv7_OP2(0xfe00, 0x1c00, T1, ADD_IMM),
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ARMv7_OP2(0xf800, 0x3000, T2, ADD_IMM),
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ARMv7_OP4(0xfbe0, 0x8000, 0xf100, 0x0000, T3, ADD_IMM, SKIP_IF( (BF(8, 11) == 15 && BT(20)) || BF(16, 19) == 13 )),
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ARMv7_OP4(0xfbf0, 0x8000, 0xf200, 0x0000, T4, ADD_IMM),
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ARMv7_OP4(0xfbf0, 0x8000, 0xf200, 0x0000, T4, ADD_IMM, SKIP_IF( (BF(16, 19) & 13) == 13 )),
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ARMv7_OP4(0x0fe0, 0x0000, 0x0280, 0x0000, A1, ADD_IMM),
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ARMv7_OP2(0xfe00, 0x1800, T1, ADD_REG),
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ARMv7_OP2(0xff00, 0x4400, T2, ADD_REG, SKIP_IF( (c & 0x87) == 0x85 || BF(3, 6) == 13 )),
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ARMv7_OP4(0xffe0, 0x8000, 0xeb00, 0x0000, T3, ADD_REG),
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ARMv7_OP4(0xffe0, 0x8000, 0xeb00, 0x0000, T3, ADD_REG, SKIP_IF( (BF(8, 11) == 15 && BT(20)) || BF(16, 19) == 13 )),
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ARMv7_OP4(0x0fe0, 0x0010, 0x0080, 0x0000, A1, ADD_REG),
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ARMv7_OP4(0x0fe0, 0x0090, 0x0080, 0x0010, A1, ADD_RSR),
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ARMv7_OP2(0xf800, 0xa800, T1, ADD_SPI),
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ARMv7_OP2(0xff80, 0xb000, T2, ADD_SPI),
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ARMv7_OP4(0xfbef, 0x8000, 0xf10d, 0x0000, T3, ADD_SPI),
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ARMv7_OP4(0xfbef, 0x8000, 0xf10d, 0x0000, T3, ADD_SPI, SKIP_IF( BF(8, 11) == 15 && BT(20) )),
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ARMv7_OP4(0xfbff, 0x8000, 0xf20d, 0x0000, T4, ADD_SPI),
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ARMv7_OP4(0x0fef, 0x0000, 0x028d, 0x0000, A1, ADD_SPI),
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ARMv7_OP2(0xff78, 0x4468, T1, ADD_SPR),
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ARMv7_OP2(0xff87, 0x4485, T2, ADD_SPR),
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ARMv7_OP2(0xff87, 0x4485, T2, ADD_SPR, SKIP_IF( BF(3, 6) == 13 )),
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ARMv7_OP4(0xffef, 0x8000, 0xeb0d, 0x0000, T3, ADD_SPR),
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ARMv7_OP4(0x0fef, 0x0010, 0x008d, 0x0000, A1, ADD_SPR),
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@ -1355,6 +1355,7 @@ void ARMv7_instrs::LDR_IMM(ARMv7Context& context, const ARMv7Code code, const AR
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reject((wback && n == t) || (t == 15 && context.ITSTATE), "UNPREDICTABLE");
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break;
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}
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case A1: throw __FUNCTION__;
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default: throw __FUNCTION__;
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}
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@ -1441,11 +1442,70 @@ void ARMv7_instrs::LDR_REG(ARMv7Context& context, const ARMv7Code code, const AR
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void ARMv7_instrs::LDRB_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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{
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u32 cond, t, n, imm32;
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bool index, add, wback;
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switch (type)
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{
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case T1:
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{
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cond = context.ITSTATE.advance();
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t = (code.data & 0x7);
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n = (code.data & 0x38) >> 3;
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imm32 = (code.data & 0x7c0) >> 4;
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index = true;
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add = true;
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wback = false;
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break;
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}
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case T2:
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{
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cond = context.ITSTATE.advance();
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t = (code.data & 0xf000) >> 12;
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n = (code.data & 0xf0000) >> 16;
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imm32 = (code.data & 0xfff);
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index = true;
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add = true;
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wback = false;
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reject(t == 15, "PLD");
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reject(n == 15, "LDRB (literal)");
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reject(t == 13, "UNPREDICTABLE");
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break;
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}
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case T3:
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{
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cond = context.ITSTATE.advance();
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t = (code.data & 0xf000) >> 12;
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n = (code.data & 0xf0000) >> 16;
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imm32 = (code.data & 0xff);
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index = (code.data & 0x400);
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add = (code.data & 0x200);
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wback = (code.data & 0x100);
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reject(t == 15 && index && !add && !wback, "PLD");
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reject(n == 15, "LDRB (literal)");
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reject(index && add && !wback, "LDRBT");
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reject(!index && !wback, "UNDEFINED");
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reject(t == 13 || t == 15 || (wback && n == t), "UNPREDICTABLE");
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break;
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}
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case A1: throw __FUNCTION__;
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default: throw __FUNCTION__;
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}
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if (ConditionPassed(context, cond))
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{
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const u32 offset_addr = add ? context.read_gpr(n) + imm32 : context.read_gpr(n) - imm32;
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const u32 addr = index ? offset_addr : context.read_gpr(n);
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context.write_gpr(t, vm::psv::read8(addr));
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if (wback)
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{
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context.write_gpr(n, offset_addr);
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}
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}
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}
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void ARMv7_instrs::LDRB_LIT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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@ -2999,11 +3059,67 @@ void ARMv7_instrs::STR_REG(ARMv7Context& context, const ARMv7Code code, const AR
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void ARMv7_instrs::STRB_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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{
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u32 cond, t, n, imm32;
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bool index, add, wback;
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switch (type)
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{
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case T1:
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{
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cond = context.ITSTATE.advance();
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t = (code.data & 0x7);
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n = (code.data & 0x38) >> 3;
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imm32 = (code.data & 0x7c0) >> 4;
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index = true;
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add = true;
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wback = false;
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break;
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}
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case T2:
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{
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cond = context.ITSTATE.advance();
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t = (code.data & 0xf000) >> 12;
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n = (code.data & 0xf0000) >> 16;
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imm32 = (code.data & 0xfff);
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index = true;
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add = true;
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wback = false;
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reject(n == 15, "UNDEFINED");
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reject(t == 13 || t == 15, "UNPREDICTABLE");
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break;
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}
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case T3:
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{
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cond = context.ITSTATE.advance();
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t = (code.data & 0xf000) >> 12;
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n = (code.data & 0xf0000) >> 16;
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imm32 = (code.data & 0xff);
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index = (code.data & 0x400);
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add = (code.data & 0x200);
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wback = (code.data & 0x100);
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reject(index && add && !wback, "STRBT");
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reject(n == 15 || (!index && !wback), "UNDEFINED");
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reject(t == 13 || t == 15 || (wback && n == t), "UNPREDICTABLE");
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break;
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}
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case A1: throw __FUNCTION__;
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default: throw __FUNCTION__;
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}
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if (ConditionPassed(context, cond))
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{
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const u32 offset_addr = add ? context.read_gpr(n) + imm32 : context.read_gpr(n) - imm32;
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const u32 addr = index ? offset_addr : context.read_gpr(n);
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vm::psv::write8(addr, (u8)context.read_gpr(t));
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if (wback)
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{
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context.write_gpr(n, offset_addr);
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}
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}
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}
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void ARMv7_instrs::STRB_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
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@ -82,4 +82,4 @@ psv_log_base sceCtrl("SceCtrl", []()
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REG_FUNC(0x15F96FB0, sceCtrlReadBufferNegative);
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REG_FUNC(0xE9CB69C8, sceCtrlSetRapidFire);
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REG_FUNC(0xD8294C9C, sceCtrlClearRapidFire);
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});
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});
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@ -6,21 +6,21 @@ extern psv_log_base sceSysmodule;
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s32 sceSysmoduleLoadModule(u16 id)
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{
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sceSysmodule.Todo("sceSysmoduleLoadModule(id=0x%04x)", id);
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sceSysmodule.Error("sceSysmoduleLoadModule(id=0x%04x) -> SCE_OK", id);
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return SCE_OK; // loading succeeded
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}
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s32 sceSysmoduleUnloadModule(u16 id)
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{
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sceSysmodule.Todo("sceSysmoduleUnloadModule(id=0x%04x)", id);
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sceSysmodule.Error("sceSysmoduleUnloadModule(id=0x%04x) -> SCE_OK", id);
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return SCE_OK; // unloading succeeded
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}
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s32 sceSysmoduleIsLoaded(u16 id)
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{
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sceSysmodule.Todo("sceSysmoduleIsLoaded(id=0x%04x)", id);
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sceSysmodule.Error("sceSysmoduleIsLoaded(id=0x%04x) -> SCE_OK", id);
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return SCE_OK; // module is loaded
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}
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