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Minor fixes
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296c931d55
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@ -73,11 +73,11 @@ namespace aarch64
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{ 0x61, 0x22, "armv8.5-a", "M1", "Firestorm" },
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{ 0x61, 0x22, "armv8.5-a", "M1", "Firestorm" },
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{ 0x61, 0x23, "armv8.5-a", "M1", "IceStorm" },
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{ 0x61, 0x23, "armv8.5-a", "M1", "IceStorm" },
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{ 0x61, 0x28, "armv8.5-a", "M1 Max", "Firestorm" },
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{ 0x61, 0x28, "armv8.5-a", "M1 Max", "Firestorm" },
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{ 0x61, 0x28, "armv8.5-a", "M1 Max", "Icestorm" },
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{ 0x61, 0x29, "armv8.5-a", "M1 Max", "Icestorm" },
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{ 0x61, 0x24, "armv8.5-a", "M1 Pro", "Firestorm" },
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{ 0x61, 0x24, "armv8.5-a", "M1 Pro", "Firestorm" },
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{ 0x61, 0x25, "armv8.5-a", "M1 Pro", "Icestorm" },
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{ 0x61, 0x25, "armv8.5-a", "M1 Pro", "Icestorm" },
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{ 0x61, 0x32, "armv8.5-a", "M2", "Avalanche" },
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{ 0x61, 0x32, "armv8.5-a", "M2", "Avalanche" },
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{ 0x61, 0x32, "armv8.5-a", "M2", "Blizzard" },
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{ 0x61, 0x33, "armv8.5-a", "M2", "Blizzard" },
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// QUALCOMM
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// QUALCOMM
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{ 0x51, 0x01, "armv8.5-a", "Snapdragon", "X-Elite" },
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{ 0x51, 0x01, "armv8.5-a", "Snapdragon", "X-Elite" },
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@ -110,10 +110,10 @@ namespace aarch64
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}
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}
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// Read main ID register
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// Read main ID register
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static u64 read_MIDR_EL1(u32 cpu_id)
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static u64 read_MIDR_EL1([[maybe_unused]] u32 cpu_id)
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{
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{
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#if defined(__linux__)
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#if defined(__linux__)
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std::string path = fmt::format("/sys/devices/system/cpu/cpu%u/regs/identification/midr_el1", cpu_id);
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const std::string path = fmt::format("/sys/devices/system/cpu/cpu%u/regs/identification/midr_el1", cpu_id);
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if (!fs::is_file(path))
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if (!fs::is_file(path))
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{
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{
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return umax;
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return umax;
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@ -54,7 +54,7 @@ namespace aarch64
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return esr_ctx ? esr_ctx->esr : 0;
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return esr_ctx ? esr_ctx->esr : 0;
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}
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}
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#else
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#else
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u64 _read_ESR_EL1(const ucontext_t* uctx)
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u64 _read_ESR_EL1(const ucontext_t*)
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{
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{
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// Unimplemented
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// Unimplemented
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return 0;
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return 0;
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