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PPU LLVM: Improve FlushRegisters
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parent
8034196c25
commit
061c92ba1f
@ -257,12 +257,15 @@ void PPUTranslator::FlushRegisters()
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{
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for (auto& local : m_locals)
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{
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const uint index = ::narrow<uint>(&local - m_locals);
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const uint index = static_cast<uint>(&local - m_locals);
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if (local && m_globals[index])
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{
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// Store value if necessary
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m_ir->CreateStore(local, m_globals[index]);
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// Don't need to store again
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m_globals[index] = nullptr;
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}
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}
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}
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@ -1609,17 +1612,13 @@ void PPUTranslator::ADDIS(ppu_opcode_t op)
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void PPUTranslator::BC(ppu_opcode_t op)
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{
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if (op.lk)
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{
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RegInit(m_lr);
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}
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const u64 target = (op.aa ? 0 : m_current_addr) + op.bt14;
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UseCondition(CheckBranchProbability(op.bo), CheckBranchCondition(op.bo, op.bi));
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if (op.lk)
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{
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RegInit(m_lr);
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m_ir->CreateStore(m_ir->getInt64(m_current_addr + 4), m_g_lr);
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}
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@ -1687,6 +1686,7 @@ void PPUTranslator::BCLR(ppu_opcode_t op)
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if (op.lk)
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{
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RegInit(m_lr);
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m_ir->CreateStore(m_ir->getInt64(m_current_addr + 4), m_g_lr);
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}
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@ -1744,17 +1744,13 @@ void PPUTranslator::CROR(ppu_opcode_t op)
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void PPUTranslator::BCCTR(ppu_opcode_t op)
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{
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if (op.lk)
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{
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RegInit(m_lr);
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}
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const auto target = RegLoad(m_ctr);
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UseCondition(CheckBranchProbability(op.bo | 0x4), CheckBranchCondition(op.bo | 0x4, op.bi));
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if (op.lk)
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{
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RegInit(m_lr);
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m_ir->CreateStore(m_ir->getInt64(m_current_addr + 4), m_g_lr);
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}
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