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- Fixed PPU G_3f_0 Decoder.

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This commit is contained in:
DH 2013-07-11 17:28:10 +03:00
parent fb57bb9c4e
commit 027a31bd84
2 changed files with 33 additions and 29 deletions
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24
rpcs3/Emu/Cell/PPUInstrTable.h
View File

@ -70,18 +70,6 @@ namespace PPU_instr
//This field is used to specify a bit in the CR, or in the FPSCR, as the destination of the result of an instruction
static CodeField<6, 10> CRBD(FIELD_R_CR);
//
static CodeField<6, 10> BT;
//
static CodeField<11, 15> BA;
//
static CodeField<16, 20> BB;
//
static CodeField<6, 10> BF;
//This field is used to specify options for the branch conditional instructions
static CodeField<6, 10> BO;
@ -158,7 +146,7 @@ namespace PPU_instr
static CodeField<6, 10> FRS;
//
static CodeField<7, 14> FLM;
static CodeField<7, 14> FM;
//This field is used to specify an FPR as a source
static CodeField<11, 15> FRA(FIELD_R_FPR);
@ -602,12 +590,12 @@ namespace PPU_instr
bind_instr(g3f_0_list, FCTID, FRD, FRB, RC);
bind_instr(g3f_0_list, FCTIDZ, FRD, FRB, RC);
bind_instr(g3f_0_list, MTFSB1, BT, RC);
bind_instr(g3f_0_list, MCRFS, BF, BFA);
bind_instr(g3f_0_list, MTFSB0, BT, RC);
bind_instr(g3f_0_list, MTFSFI, CRFD, I, RC);
bind_instr(g3f_0_list, MTFSB1, CRBD, RC);
bind_instr(g3f_0_list, MCRFS, CRFD, CRFS);
bind_instr(g3f_0_list, MTFSB0, CRBD, RC);
bind_instr(g3f_0_list, MTFSFI, CRBD, I, RC);
bind_instr(g3f_0_list, MFFS, FRD, RC);
bind_instr(g3f_0_list, MTFSF, FLM, FRB, RC);
bind_instr(g3f_0_list, MTFSF, FM, FRB, RC);
#undef bind_instr
};

38
rpcs3/Emu/Cell/PPUInterpreter.h
View File

@ -3286,26 +3286,42 @@ private:
Memory.Write64(addr, CPU.GPR[rs]);
CPU.GPR[ra] = addr;
}
void MTFSB1(u32 bt, bool rc)
void MTFSB1(u32 crbd, bool rc)
{
UNIMPLEMENTED();
u64 mask = (1ULL << crbd);
CPU.FPSCR.FPSCR |= mask;
if(rc) UNIMPLEMENTED();
}
void MCRFS(u32 bf, u32 bfa)
void MCRFS(u32 crbd, u32 crbs)
{
UNIMPLEMENTED();
u64 mask = (1ULL << crbd);
CPU.CR.CR &= ~mask;
CPU.CR.CR |= CPU.FPSCR.FPSCR & mask;
}
void MTFSB0(u32 bt, bool rc)
void MTFSB0(u32 crbd, bool rc)
{
UNIMPLEMENTED();
u64 mask = (1ULL << crbd);
CPU.FPSCR.FPSCR &= ~mask;
if(rc) UNIMPLEMENTED();
}
void MTFSFI(u32 crfd, u32 i, bool rc)
{
UNIMPLEMENTED();
u64 mask = (1ULL << crfd);
if(i)
{
CPU.FPSCR.FPSCR |= mask;
}
else
{
CPU.FPSCR.FPSCR &= ~mask;
}
if(rc) UNIMPLEMENTED();
}
void MFFS(u32 frd, bool rc)
{
(u64&)CPU.FPR[frd] = CPU.FPSCR.FPSCR;
if(rc) UNK("mffs.");
if(rc) UNIMPLEMENTED();
}
void MTFSF(u32 flm, u32 frb, bool rc)
{
@ -3493,17 +3509,17 @@ private:
CPU.FPR[frd] = CPU.FPR[fra] * CPU.FPR[frc];
CPU.FPSCR.FI = 0;
CPU.FPSCR.FR = 0;
CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType();
CPU.FPSCR.FPRF = CPU.FPR[frd].GetType();
if(rc) UNK("fmul.");//CPU.UpdateCR1(CPU.FPR[frd]);
}
void FRSQRTE(u32 frd, u32 frb, bool rc)
{
UNIMPLEMENTED();
//if(CPU.FPR[frb].
}
void FMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc)
{
CPU.FPR[frd] = CPU.FPR[fra] * CPU.FPR[frc] - CPU.FPR[frb];
CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType();
CPU.FPSCR.FPRF = CPU.FPR[frd].GetType();
if(rc) UNK("fmsub.");//CPU.UpdateCR1(CPU.FPR[frd]);
}
void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc)