Commit Graph

63 Commits

Author SHA1 Message Date
angie
baf3ce83ee Fix missing braces warning 2022-09-09 23:19:45 -04:00
angie
ea935b8358 refactor operand names 2022-09-09 23:13:23 -04:00
Anghelo Carvajal
136fb7a09a
Add R5900 support (#5)
* starting r5900 stuff

* operands of pmaddh

* expose R5900 to python

* fix merge issues

* move to subtables

* mmi0 and mmi3

* the rest of mmi instructions

* normal, special, regimm and cop0

* fpu_s

* cop2 special1

* starting cop2 special2

* the rest of special2

* operands for normal, special, mmi and mmi0

* mmi1 and mmi2

* Fix mmi

* sync.p

* mmi3 and cop1

* add r5900 opcodes to InstrId.pyi

* add invalid bits to unknown instruction comment

* progress on cop2 special1

* kinda finish cop2 special1

* cop2 special2 progress

* Special case for R5900 cvt.w.s -> trunc.w.s

* R5900 c.olt.s and c.ole.s

* Fix a bunch of VU0 instructions

* I'm getting tired of this bullshit

* vlqi, vsqi, vlqd, vsqd

* fix some operands

* fix div1

* lqc2 and sqc2

* sqrt.s and mult

* fix mtsa and bc2

* Remove redundant .instrType=RABBITIZER_INSTR_TYPE_UNKNOWN

* RabbitizerInstrSuffix

* Impleme instr suffix type

* add instr suffix to remaining instructions

* ifdef out xyzw suffix from registers

* format

* fix warnings

* uncomment stuff on InstrId.pyi

* readme
2022-08-27 12:22:48 -04:00
Angie
d4cb445cc1 Add -Wpedantic to makefile 2022-08-23 15:12:55 -04:00
Angie
c9a9845a65 finish up rsp tables 2022-08-23 15:07:25 -04:00
Angie
75e129b3dd make tables for rsp normal, special, regimm and cop0 2022-08-23 14:06:52 -04:00
Angie
5b59b2dff7 finish up cpu instructions 2022-08-23 12:31:03 -04:00
Angie
2ebb5f7712 Tables for cpu except cop1 2022-08-23 10:55:14 -04:00
Angie
5ec08f914d Start including the case bits on the tables themselves 2022-08-23 09:32:24 -04:00
Anghelo Carvajal
f8979ede3e
Fix RSP instruction decoding (#4)
* Use the proper registers on RSP GPR instructions

* Add IMM_base operand to RSP instructions

* Use `ra` on RSP GPR registers

* Fix RABBITIZER_OPERAND_TYPE_RSP_rd

* ??

* fix vector register element index

* fix RSP mfc2 and mtc2

* fix vmov and similar instructions

* format

* update readme

* version pump
2022-08-22 16:27:51 -04:00
angie
a539a8a39d Annotate functions with attributes 2022-07-09 19:19:53 -04:00
angie
ef1ce2634c add more checks to clang tidy 2022-07-09 18:12:21 -04:00
angie
ecc8de8df2 Add a makefile for testing and fix one warning 2022-07-09 16:54:42 -04:00
angie
b3ffb7a713 Rename isHiPair and isLoPair to canBeHi and canBeLo 2022-07-07 15:48:10 -04:00
angie
dc314098d0 hasDelaySlot 2022-07-07 15:12:26 -04:00
angie
19579a183a Allow pickling Instruction type 2022-07-07 14:22:41 -04:00
Angie
c129447463 getProcessedImmediate 2022-07-06 20:12:37 -04:00
Angie
6fc7be4517 RabbitizerInstruction_disassembleOperands 2022-07-06 19:17:29 -04:00
angie
55de30256a doesLoad and doesStore 2022-07-05 13:32:24 -04:00
angie
63591003f6 RabbitizerInstruction_hasOperandAlias 2022-07-05 09:18:48 -04:00
Angie
568a0662f2 remove redundant functions 2022-07-05 00:53:28 -04:00
Angie
bed5d928dd RabbitizerInstruction_isValid 2022-07-03 19:28:13 -04:00
Angie
a725e0281a minor cleanups 2022-07-03 11:34:46 -04:00
Angie
0c678ab6df remove specific registers from instruction struct
do bitwise operations to access them instead
2022-07-03 08:34:26 -04:00
Angie
d0b39c6f8c introduce macros for reading the bits from the instruction word 2022-07-02 18:49:05 -04:00
angie
1b67fe86dd expose some more descriptor methods to python 2022-07-01 12:57:58 -04:00
angie
7eab5eb1df Add architecture version to most cpu instructions
fp instructions are not done yet
2022-07-01 12:07:45 -04:00
angie
b3843f271e starting to port RegistersTracker 2022-06-11 17:49:33 -04:00
angie
cca3a10100 Expose InstrCategory enum to python 2022-06-09 12:06:49 -04:00
angie
8b37e56e2e Some fixes 2022-06-08 22:44:43 -04:00
angie
bab16d24a5 Add more stuff to Descriptor 2022-06-08 02:17:48 -04:00
angie
d68751a1f9 Rename RabbitizerInstr to RabbitizerInstruction 2022-06-08 00:30:58 -04:00
angie
9c05b19866 rename RabbitizerRegisterType to RabbitizerOperandType 2022-06-07 23:30:01 -04:00
angie
118ee1cc89 rsp 2022-06-07 03:16:09 -04:00
angie
518953980c more rsp stuff 2022-06-07 02:28:10 -04:00
angie
9b4ac24ca5 macro abuse on Disassemble 2022-06-07 00:49:37 -04:00
angie
ca3823888c another rsp batch 2022-06-06 22:42:22 -04:00
angie
185a934081 First batch of rsp stuff 2022-06-06 22:19:42 -04:00
angie
7125a90d62 blankOut and sameOpcode 2022-06-06 02:02:27 -04:00
angie
b561f3f4b9 Rename the instr id enums 2022-06-05 19:15:25 -04:00
angie
6b7650476f Change capitalization 2022-06-05 13:19:45 -04:00
angie
b01fc41a5a Moving stuff around 2022-06-05 12:25:57 -04:00
angie
d7c154e293 Implement MapInstrToType 2022-06-05 12:05:06 -04:00
angie
4cbc14c813 FpcCsr 2022-06-05 02:19:05 -04:00
angie
145114c096 toggle register names 2022-06-05 01:57:22 -04:00
angie
6a0cdbb637 more stuff 2022-06-04 23:23:06 -04:00
angie
55b016488a implementing some missing functions and some bugfixes 2022-06-04 22:18:53 -04:00
angie
97fd189cda RSP instr id enum placeholder 2022-06-04 17:40:16 -04:00
angie
f5c3f7ce2d Move instruction id definitions to common macros 2022-06-04 17:34:17 -04:00
angie
85bf2c887a Convert extraLjustWidthOpcode to a parameter 2022-06-04 12:43:54 -04:00