mirror of
https://github.com/raspberrypi/pico-sdk.git
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68571ad33e
* Use reg[0] description for hardware structs register arrays * Update struct headers to match SVD and latest svd2struct
327 lines
13 KiB
C
327 lines
13 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/*
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* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_CLOCKS_H
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#define _HARDWARE_STRUCTS_CLOCKS_H
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#include "hardware/address_mapped.h"
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#include "hardware/regs/clocks.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_clocks
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/clocks.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
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/*! \brief Enumeration identifying a hardware clock
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* \ingroup hardware_clocks
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*/
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/// \tag::clkenum[]
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enum clock_index {
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clk_gpout0 = 0, ///< GPIO Muxing 0
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clk_gpout1, ///< GPIO Muxing 1
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clk_gpout2, ///< GPIO Muxing 2
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clk_gpout3, ///< GPIO Muxing 3
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clk_ref, ///< Watchdog and timers reference clock
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clk_sys, ///< Processors, bus fabric, memory, memory mapped registers
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clk_peri, ///< Peripheral clock for UART and SPI
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clk_usb, ///< USB clock
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clk_adc, ///< ADC clock
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clk_rtc, ///< Real time clock
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CLK_COUNT
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};
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/// \end::clkenum[]
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/// \tag::clock_hw[]
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typedef struct {
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_REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL
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// Clock control, can be changed on-the-fly (except for auxsrc)
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// 0x00100000 [20] : NUDGE (0): An edge on this signal shifts the phase of the output by 1 cycle of the input clock
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// 0x00030000 [17:16] : PHASE (0): This delays the enable signal by up to 3 cycles of the input clock
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// 0x00001000 [12] : DC50 (0): Enables duty cycle correction for odd divisors
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// 0x00000800 [11] : ENABLE (0): Starts and stops the clock generator cleanly
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// 0x00000400 [10] : KILL (0): Asynchronously kills the clock generator
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// 0x000001e0 [8:5] : AUXSRC (0): Selects the auxiliary clock source, will glitch when switching
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io_rw_32 ctrl;
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_REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV
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// Clock divisor, can be changed on-the-fly
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// 0xffffff00 [31:8] : INT (1): Integer component of the divisor, 0 -> divide by 2^16
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// 0x000000ff [7:0] : FRAC (0): Fractional component of the divisor
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io_rw_32 div;
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_REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED
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// Indicates which SRC is currently selected by the glitchless mux (one-hot)
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io_ro_32 selected;
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} clock_hw_t;
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/// \end::clock_hw[]
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typedef struct {
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_REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL
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// 0x00010000 [16] : CLEAR (0): For clearing the resus after the fault that triggered it has been corrected
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// 0x00001000 [12] : FRCE (0): Force a resus, for test purposes only
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// 0x00000100 [8] : ENABLE (0): Enable resus
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// 0x000000ff [7:0] : TIMEOUT (0xff): This is expressed as a number of clk_ref cycles
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io_rw_32 ctrl;
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_REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS
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// 0x00000001 [0] : RESUSSED (0): Clock has been resuscitated, correct the error then send ctrl_clear=1
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io_ro_32 status;
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} clock_resus_hw_t;
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typedef struct {
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_REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ
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// Reference clock frequency in kHz
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// 0x000fffff [19:0] : FC0_REF_KHZ (0)
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io_rw_32 ref_khz;
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_REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ
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// Minimum pass frequency in kHz
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// 0x01ffffff [24:0] : FC0_MIN_KHZ (0)
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io_rw_32 min_khz;
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_REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ
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// Maximum pass frequency in kHz
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// 0x01ffffff [24:0] : FC0_MAX_KHZ (0x1ffffff)
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io_rw_32 max_khz;
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_REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY
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// Delays the start of frequency counting to allow the mux to settle
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// 0x00000007 [2:0] : FC0_DELAY (1)
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io_rw_32 delay;
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_REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL
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// The test interval is 0
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// 0x0000000f [3:0] : FC0_INTERVAL (0x8)
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io_rw_32 interval;
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_REG_(CLOCKS_FC0_SRC_OFFSET) // CLOCKS_FC0_SRC
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// Clock sent to frequency counter, set to 0 when not required
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// 0x000000ff [7:0] : FC0_SRC (0)
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io_rw_32 src;
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_REG_(CLOCKS_FC0_STATUS_OFFSET) // CLOCKS_FC0_STATUS
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// Frequency counter status
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// 0x10000000 [28] : DIED (0): Test clock stopped during test
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// 0x01000000 [24] : FAST (0): Test clock faster than expected, only valid when status_done=1
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// 0x00100000 [20] : SLOW (0): Test clock slower than expected, only valid when status_done=1
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// 0x00010000 [16] : FAIL (0): Test failed
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// 0x00001000 [12] : WAITING (0): Waiting for test clock to start
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// 0x00000100 [8] : RUNNING (0): Test running
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// 0x00000010 [4] : DONE (0): Test complete
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// 0x00000001 [0] : PASS (0): Test passed
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io_ro_32 status;
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_REG_(CLOCKS_FC0_RESULT_OFFSET) // CLOCKS_FC0_RESULT
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// Result of frequency measurement, only valid when status_done=1
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// 0x3fffffe0 [29:5] : KHZ (0)
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// 0x0000001f [4:0] : FRAC (0)
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io_ro_32 result;
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} fc_hw_t;
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typedef struct {
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clock_hw_t clk[CLK_COUNT]; // 10
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clock_resus_hw_t resus;
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fc_hw_t fc0;
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_REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0
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// enable clock in wake mode
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// 0x80000000 [31] : clk_sys_sram3 (1)
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// 0x40000000 [30] : clk_sys_sram2 (1)
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// 0x20000000 [29] : clk_sys_sram1 (1)
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// 0x10000000 [28] : clk_sys_sram0 (1)
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// 0x08000000 [27] : clk_sys_spi1 (1)
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// 0x04000000 [26] : clk_peri_spi1 (1)
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// 0x02000000 [25] : clk_sys_spi0 (1)
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// 0x01000000 [24] : clk_peri_spi0 (1)
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// 0x00800000 [23] : clk_sys_sio (1)
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// 0x00400000 [22] : clk_sys_rtc (1)
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// 0x00200000 [21] : clk_rtc_rtc (1)
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// 0x00100000 [20] : clk_sys_rosc (1)
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// 0x00080000 [19] : clk_sys_rom (1)
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// 0x00040000 [18] : clk_sys_resets (1)
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// 0x00020000 [17] : clk_sys_pwm (1)
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// 0x00010000 [16] : clk_sys_psm (1)
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// 0x00008000 [15] : clk_sys_pll_usb (1)
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// 0x00004000 [14] : clk_sys_pll_sys (1)
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// 0x00002000 [13] : clk_sys_pio1 (1)
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// 0x00001000 [12] : clk_sys_pio0 (1)
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// 0x00000800 [11] : clk_sys_pads (1)
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// 0x00000400 [10] : clk_sys_vreg_and_chip_reset (1)
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// 0x00000200 [9] : clk_sys_jtag (1)
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// 0x00000100 [8] : clk_sys_io (1)
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// 0x00000080 [7] : clk_sys_i2c1 (1)
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// 0x00000040 [6] : clk_sys_i2c0 (1)
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// 0x00000020 [5] : clk_sys_dma (1)
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// 0x00000010 [4] : clk_sys_busfabric (1)
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// 0x00000008 [3] : clk_sys_busctrl (1)
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// 0x00000004 [2] : clk_sys_adc (1)
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// 0x00000002 [1] : clk_adc_adc (1)
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// 0x00000001 [0] : clk_sys_clocks (1)
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io_rw_32 wake_en0;
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_REG_(CLOCKS_WAKE_EN1_OFFSET) // CLOCKS_WAKE_EN1
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// enable clock in wake mode
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// 0x00004000 [14] : clk_sys_xosc (1)
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// 0x00002000 [13] : clk_sys_xip (1)
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// 0x00001000 [12] : clk_sys_watchdog (1)
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// 0x00000800 [11] : clk_usb_usbctrl (1)
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// 0x00000400 [10] : clk_sys_usbctrl (1)
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// 0x00000200 [9] : clk_sys_uart1 (1)
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// 0x00000100 [8] : clk_peri_uart1 (1)
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// 0x00000080 [7] : clk_sys_uart0 (1)
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// 0x00000040 [6] : clk_peri_uart0 (1)
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// 0x00000020 [5] : clk_sys_timer (1)
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// 0x00000010 [4] : clk_sys_tbman (1)
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// 0x00000008 [3] : clk_sys_sysinfo (1)
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// 0x00000004 [2] : clk_sys_syscfg (1)
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// 0x00000002 [1] : clk_sys_sram5 (1)
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// 0x00000001 [0] : clk_sys_sram4 (1)
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io_rw_32 wake_en1;
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_REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0
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// enable clock in sleep mode
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// 0x80000000 [31] : clk_sys_sram3 (1)
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// 0x40000000 [30] : clk_sys_sram2 (1)
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// 0x20000000 [29] : clk_sys_sram1 (1)
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// 0x10000000 [28] : clk_sys_sram0 (1)
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// 0x08000000 [27] : clk_sys_spi1 (1)
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// 0x04000000 [26] : clk_peri_spi1 (1)
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// 0x02000000 [25] : clk_sys_spi0 (1)
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// 0x01000000 [24] : clk_peri_spi0 (1)
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// 0x00800000 [23] : clk_sys_sio (1)
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// 0x00400000 [22] : clk_sys_rtc (1)
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// 0x00200000 [21] : clk_rtc_rtc (1)
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// 0x00100000 [20] : clk_sys_rosc (1)
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// 0x00080000 [19] : clk_sys_rom (1)
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// 0x00040000 [18] : clk_sys_resets (1)
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// 0x00020000 [17] : clk_sys_pwm (1)
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// 0x00010000 [16] : clk_sys_psm (1)
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// 0x00008000 [15] : clk_sys_pll_usb (1)
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// 0x00004000 [14] : clk_sys_pll_sys (1)
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// 0x00002000 [13] : clk_sys_pio1 (1)
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// 0x00001000 [12] : clk_sys_pio0 (1)
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// 0x00000800 [11] : clk_sys_pads (1)
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// 0x00000400 [10] : clk_sys_vreg_and_chip_reset (1)
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// 0x00000200 [9] : clk_sys_jtag (1)
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// 0x00000100 [8] : clk_sys_io (1)
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// 0x00000080 [7] : clk_sys_i2c1 (1)
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// 0x00000040 [6] : clk_sys_i2c0 (1)
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// 0x00000020 [5] : clk_sys_dma (1)
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// 0x00000010 [4] : clk_sys_busfabric (1)
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// 0x00000008 [3] : clk_sys_busctrl (1)
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// 0x00000004 [2] : clk_sys_adc (1)
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// 0x00000002 [1] : clk_adc_adc (1)
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// 0x00000001 [0] : clk_sys_clocks (1)
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io_rw_32 sleep_en0;
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_REG_(CLOCKS_SLEEP_EN1_OFFSET) // CLOCKS_SLEEP_EN1
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// enable clock in sleep mode
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// 0x00004000 [14] : clk_sys_xosc (1)
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// 0x00002000 [13] : clk_sys_xip (1)
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// 0x00001000 [12] : clk_sys_watchdog (1)
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// 0x00000800 [11] : clk_usb_usbctrl (1)
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// 0x00000400 [10] : clk_sys_usbctrl (1)
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// 0x00000200 [9] : clk_sys_uart1 (1)
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// 0x00000100 [8] : clk_peri_uart1 (1)
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// 0x00000080 [7] : clk_sys_uart0 (1)
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// 0x00000040 [6] : clk_peri_uart0 (1)
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// 0x00000020 [5] : clk_sys_timer (1)
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// 0x00000010 [4] : clk_sys_tbman (1)
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// 0x00000008 [3] : clk_sys_sysinfo (1)
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// 0x00000004 [2] : clk_sys_syscfg (1)
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// 0x00000002 [1] : clk_sys_sram5 (1)
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// 0x00000001 [0] : clk_sys_sram4 (1)
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io_rw_32 sleep_en1;
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_REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0
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// indicates the state of the clock enable
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// 0x80000000 [31] : clk_sys_sram3 (0)
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// 0x40000000 [30] : clk_sys_sram2 (0)
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// 0x20000000 [29] : clk_sys_sram1 (0)
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// 0x10000000 [28] : clk_sys_sram0 (0)
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// 0x08000000 [27] : clk_sys_spi1 (0)
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// 0x04000000 [26] : clk_peri_spi1 (0)
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// 0x02000000 [25] : clk_sys_spi0 (0)
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// 0x01000000 [24] : clk_peri_spi0 (0)
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// 0x00800000 [23] : clk_sys_sio (0)
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// 0x00400000 [22] : clk_sys_rtc (0)
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// 0x00200000 [21] : clk_rtc_rtc (0)
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// 0x00100000 [20] : clk_sys_rosc (0)
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// 0x00080000 [19] : clk_sys_rom (0)
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// 0x00040000 [18] : clk_sys_resets (0)
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// 0x00020000 [17] : clk_sys_pwm (0)
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// 0x00010000 [16] : clk_sys_psm (0)
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// 0x00008000 [15] : clk_sys_pll_usb (0)
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// 0x00004000 [14] : clk_sys_pll_sys (0)
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// 0x00002000 [13] : clk_sys_pio1 (0)
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// 0x00001000 [12] : clk_sys_pio0 (0)
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// 0x00000800 [11] : clk_sys_pads (0)
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// 0x00000400 [10] : clk_sys_vreg_and_chip_reset (0)
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// 0x00000200 [9] : clk_sys_jtag (0)
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// 0x00000100 [8] : clk_sys_io (0)
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// 0x00000080 [7] : clk_sys_i2c1 (0)
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// 0x00000040 [6] : clk_sys_i2c0 (0)
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// 0x00000020 [5] : clk_sys_dma (0)
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// 0x00000010 [4] : clk_sys_busfabric (0)
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// 0x00000008 [3] : clk_sys_busctrl (0)
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// 0x00000004 [2] : clk_sys_adc (0)
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// 0x00000002 [1] : clk_adc_adc (0)
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// 0x00000001 [0] : clk_sys_clocks (0)
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io_ro_32 enabled0;
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_REG_(CLOCKS_ENABLED1_OFFSET) // CLOCKS_ENABLED1
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// indicates the state of the clock enable
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// 0x00004000 [14] : clk_sys_xosc (0)
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// 0x00002000 [13] : clk_sys_xip (0)
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// 0x00001000 [12] : clk_sys_watchdog (0)
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// 0x00000800 [11] : clk_usb_usbctrl (0)
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// 0x00000400 [10] : clk_sys_usbctrl (0)
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// 0x00000200 [9] : clk_sys_uart1 (0)
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// 0x00000100 [8] : clk_peri_uart1 (0)
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// 0x00000080 [7] : clk_sys_uart0 (0)
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// 0x00000040 [6] : clk_peri_uart0 (0)
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// 0x00000020 [5] : clk_sys_timer (0)
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// 0x00000010 [4] : clk_sys_tbman (0)
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// 0x00000008 [3] : clk_sys_sysinfo (0)
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// 0x00000004 [2] : clk_sys_syscfg (0)
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// 0x00000002 [1] : clk_sys_sram5 (0)
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// 0x00000001 [0] : clk_sys_sram4 (0)
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io_ro_32 enabled1;
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_REG_(CLOCKS_INTR_OFFSET) // CLOCKS_INTR
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// Raw Interrupts
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// 0x00000001 [0] : CLK_SYS_RESUS (0)
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io_ro_32 intr;
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_REG_(CLOCKS_INTE_OFFSET) // CLOCKS_INTE
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// Interrupt Enable
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// 0x00000001 [0] : CLK_SYS_RESUS (0)
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io_rw_32 inte;
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_REG_(CLOCKS_INTF_OFFSET) // CLOCKS_INTF
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// Interrupt Force
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// 0x00000001 [0] : CLK_SYS_RESUS (0)
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io_rw_32 intf;
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_REG_(CLOCKS_INTS_OFFSET) // CLOCKS_INTS
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// Interrupt status after masking & forcing
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// 0x00000001 [0] : CLK_SYS_RESUS (0)
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io_ro_32 ints;
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} clocks_hw_t;
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#define clocks_hw ((clocks_hw_t *const)CLOCKS_BASE)
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static_assert( CLK_COUNT == 10, "");
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#endif
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