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https://github.com/raspberrypi/pico-sdk.git
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0562089fab
* fix __force_inline for different GCC versions in cpp mode (the affected versions are different from c mode), and build kitchsink.c as a cpp file too for testing * silly bug in host platform.h
61 lines
2.1 KiB
C
61 lines
2.1 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/*
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* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_XOSC_H
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#define _HARDWARE_STRUCTS_XOSC_H
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#include "hardware/address_mapped.h"
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#include "hardware/regs/xosc.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xosc
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/xosc.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
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/// \tag::xosc_hw[]
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typedef struct {
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_REG_(XOSC_CTRL_OFFSET) // XOSC_CTRL
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// Crystal Oscillator Control
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// 0x00fff000 [23:12] : ENABLE (0): On power-up this field is initialised to DISABLE and the chip runs from the ROSC
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// 0x00000fff [11:0] : FREQ_RANGE (0): Frequency range
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io_rw_32 ctrl;
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_REG_(XOSC_STATUS_OFFSET) // XOSC_STATUS
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// Crystal Oscillator Status
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// 0x80000000 [31] : STABLE (0): Oscillator is running and stable
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// 0x01000000 [24] : BADWRITE (0): An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT
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// 0x00001000 [12] : ENABLED (0): Oscillator is enabled but not necessarily running and stable, resets to 0
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// 0x00000003 [1:0] : FREQ_RANGE (0): The current frequency range setting, always reads 0
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io_rw_32 status;
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_REG_(XOSC_DORMANT_OFFSET) // XOSC_DORMANT
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// Crystal Oscillator pause control
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io_rw_32 dormant;
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_REG_(XOSC_STARTUP_OFFSET) // XOSC_STARTUP
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// Controls the startup delay
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// 0x00100000 [20] : X4 (0): Multiplies the startup_delay by 4
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// 0x00003fff [13:0] : DELAY (0xc4): in multiples of 256*xtal_period
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io_rw_32 startup;
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uint32_t _pad0[3];
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_REG_(XOSC_COUNT_OFFSET) // XOSC_COUNT
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// A down counter running at the xosc frequency which counts to zero and stops
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// 0x000000ff [7:0] : COUNT (0)
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io_rw_32 count;
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} xosc_hw_t;
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#define xosc_hw ((xosc_hw_t *)XOSC_BASE)
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/// \end::xosc_hw[]
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#endif
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