mirror/mbedtls
1
0
Fork 0
mirror of https://github.com/Mbed-TLS/mbedtls.git synced 2025-04-17 20:42:44 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Merge pull request #7651 from daverodgman/fix-armclang-compile-fail

Browse Source 
Fix armclang compile fail
This commit is contained in:
Gilles Peskine 2023-06-08 14:36:18 +02:00 committed by GitHub
commit 95b43a04a9
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 85 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
ChangeLog.d/armclang-compile-fix.txt Normal file
View File

@ -0,0 +1,7 @@
Bugfix
* Fix clang and armclang compilation error when targeting certain Arm
M-class CPUs (Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M23,
SecurCore SC000). Fixes #1077.
Changes
* Enable Arm / Thumb bignum assembly for most Arm platforms when
compiling with gcc, clang or armclang and -O0.

78
library/bn_mul.h
View File

@ -658,6 +658,20 @@
#endif /* TriCore */ #endif /* TriCore */
#if defined(__arm__)
#if defined(__thumb__) && !defined(__thumb2__)
#if !defined(__ARMCC_VERSION) && !defined(__clang__) \
&& !defined(__llvm__) && !defined(__INTEL_COMPILER)
/*
* Thumb 1 ISA. This code path has only been tested successfully on gcc;
* it does not compile on clang or armclang.
*
* Other compilers which define __GNUC__ may not work. The above macro
* attempts to exclude these untested compilers.
*/
#if !defined(__OPTIMIZE__) && defined(__GNUC__)
/* /*
* Note, gcc -O0 by default uses r7 for the frame pointer, so it complains about * Note, gcc -O0 by default uses r7 for the frame pointer, so it complains about
* our use of r7 below, unless -fomit-frame-pointer is passed. * our use of r7 below, unless -fomit-frame-pointer is passed.
@ -666,32 +680,39 @@
* x !=0, which we can detect using __OPTIMIZE__ (which is also defined by * x !=0, which we can detect using __OPTIMIZE__ (which is also defined by
* clang and armcc5 under the same conditions). * clang and armcc5 under the same conditions).
* *
* So, only use the optimized assembly below for optimized build, which avoids * If gcc needs to use r7, we use r1 as a scratch register and have a few extra
* the build error and is pretty reasonable anyway. * instructions to preserve/restore it; otherwise, we can use r7 and avoid
* the preserve/restore overhead.
*/ */
#if defined(__GNUC__) && !defined(__OPTIMIZE__) #define MULADDC_SCRATCH "RS .req r1 \n\t"
#define MULADDC_CANNOT_USE_R7 #define MULADDC_PRESERVE_SCRATCH "mov r10, r1 \n\t"
#endif #define MULADDC_RESTORE_SCRATCH "mov r1, r10 \n\t"
#define MULADDC_SCRATCH_CLOBBER "r10"
#if defined(__arm__) && !defined(MULADDC_CANNOT_USE_R7) #else /* !defined(__OPTIMIZE__) && defined(__GNUC__) */
#define MULADDC_SCRATCH "RS .req r7 \n\t"
#if defined(__thumb__) && !defined(__thumb2__) #define MULADDC_PRESERVE_SCRATCH ""
#define MULADDC_RESTORE_SCRATCH ""
#define MULADDC_SCRATCH_CLOBBER "r7"
#endif /* !defined(__OPTIMIZE__) && defined(__GNUC__) */
#define MULADDC_X1_INIT \ #define MULADDC_X1_INIT \
asm( \ asm( \
MULADDC_SCRATCH \
"ldr r0, %3 \n\t" \ "ldr r0, %3 \n\t" \
"ldr r1, %4 \n\t" \ "ldr r1, %4 \n\t" \
"ldr r2, %5 \n\t" \ "ldr r2, %5 \n\t" \
"ldr r3, %6 \n\t" \ "ldr r3, %6 \n\t" \
"lsr r7, r3, #16 \n\t" \ "lsr r4, r3, #16 \n\t" \
"mov r9, r7 \n\t" \ "mov r9, r4 \n\t" \
"lsl r7, r3, #16 \n\t" \ "lsl r4, r3, #16 \n\t" \
"lsr r7, r7, #16 \n\t" \ "lsr r4, r4, #16 \n\t" \
"mov r8, r7 \n\t" "mov r8, r4 \n\t" \
#define MULADDC_X1_CORE \ #define MULADDC_X1_CORE \
MULADDC_PRESERVE_SCRATCH \
"ldmia r0!, {r6} \n\t" \ "ldmia r0!, {r6} \n\t" \
"lsr r7, r6, #16 \n\t" \ "lsr RS, r6, #16 \n\t" \
"lsl r6, r6, #16 \n\t" \ "lsl r6, r6, #16 \n\t" \
"lsr r6, r6, #16 \n\t" \ "lsr r6, r6, #16 \n\t" \
"mov r4, r8 \n\t" \ "mov r4, r8 \n\t" \
@ -699,12 +720,12 @@
"mov r3, r9 \n\t" \ "mov r3, r9 \n\t" \
"mul r6, r3 \n\t" \ "mul r6, r3 \n\t" \
"mov r5, r9 \n\t" \ "mov r5, r9 \n\t" \
"mul r5, r7 \n\t" \ "mul r5, RS \n\t" \
"mov r3, r8 \n\t" \ "mov r3, r8 \n\t" \
"mul r7, r3 \n\t" \ "mul RS, r3 \n\t" \
"lsr r3, r6, #16 \n\t" \ "lsr r3, r6, #16 \n\t" \
"add r5, r5, r3 \n\t" \ "add r5, r5, r3 \n\t" \
"lsr r3, r7, #16 \n\t" \ "lsr r3, RS, #16 \n\t" \
"add r5, r5, r3 \n\t" \ "add r5, r5, r3 \n\t" \
"add r4, r4, r2 \n\t" \ "add r4, r4, r2 \n\t" \
"mov r2, #0 \n\t" \ "mov r2, #0 \n\t" \
@ -712,9 +733,10 @@
"lsl r3, r6, #16 \n\t" \ "lsl r3, r6, #16 \n\t" \
"add r4, r4, r3 \n\t" \ "add r4, r4, r3 \n\t" \
"adc r5, r2 \n\t" \ "adc r5, r2 \n\t" \
"lsl r3, r7, #16 \n\t" \ "lsl r3, RS, #16 \n\t" \
"add r4, r4, r3 \n\t" \ "add r4, r4, r3 \n\t" \
"adc r5, r2 \n\t" \ "adc r5, r2 \n\t" \
MULADDC_RESTORE_SCRATCH \
"ldr r3, [r1] \n\t" \ "ldr r3, [r1] \n\t" \
"add r4, r4, r3 \n\t" \ "add r4, r4, r3 \n\t" \
"adc r2, r5 \n\t" \ "adc r2, r5 \n\t" \
@ -727,11 +749,15 @@
: "=m" (c), "=m" (d), "=m" (s) \ : "=m" (c), "=m" (d), "=m" (s) \
: "m" (s), "m" (d), "m" (c), "m" (b) \ : "m" (s), "m" (d), "m" (c), "m" (b) \
: "r0", "r1", "r2", "r3", "r4", "r5", \ : "r0", "r1", "r2", "r3", "r4", "r5", \
"r6", "r7", "r8", "r9", "cc" \ "r6", MULADDC_SCRATCH_CLOBBER, "r8", "r9", "cc" \
); );
#endif /* !defined(__ARMCC_VERSION) && !defined(__clang__) */
#elif (__ARM_ARCH >= 6) && \ #elif (__ARM_ARCH >= 6) && \
defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1) defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)
/* Armv6-M (or later) with DSP Instruction Set Extensions.
* Requires support for either Thumb 2 or Arm ISA.
*/
#define MULADDC_X1_INIT \ #define MULADDC_X1_INIT \
{ \ { \
@ -796,7 +822,7 @@
); \ ); \
} }
#else #else /* Thumb 2 or Arm ISA, without DSP extensions */
#define MULADDC_X1_INIT \ #define MULADDC_X1_INIT \
asm( \ asm( \
@ -810,9 +836,9 @@
"mov r5, #0 \n\t" \ "mov r5, #0 \n\t" \
"ldr r6, [r1] \n\t" \ "ldr r6, [r1] \n\t" \
"umlal r2, r5, r3, r4 \n\t" \ "umlal r2, r5, r3, r4 \n\t" \
"adds r7, r6, r2 \n\t" \ "adds r4, r6, r2 \n\t" \
"adc r2, r5, #0 \n\t" \ "adc r2, r5, #0 \n\t" \
"str r7, [r1], #4 \n\t" "str r4, [r1], #4 \n\t"
#define MULADDC_X1_STOP \ #define MULADDC_X1_STOP \
"str r2, %0 \n\t" \ "str r2, %0 \n\t" \
@ -821,12 +847,12 @@
: "=m" (c), "=m" (d), "=m" (s) \ : "=m" (c), "=m" (d), "=m" (s) \
: "m" (s), "m" (d), "m" (c), "m" (b) \ : "m" (s), "m" (d), "m" (c), "m" (b) \
: "r0", "r1", "r2", "r3", "r4", "r5", \ : "r0", "r1", "r2", "r3", "r4", "r5", \
"r6", "r7", "cc" \ "r6", "cc" \
); );
#endif /* Thumb */ #endif /* ISA codepath selection */
#endif /* ARMv3 */ #endif /* defined(__arm__) */
#if defined(__alpha__) #if defined(__alpha__)

27
tests/scripts/all.sh
View File

@ -3895,6 +3895,25 @@ component_build_arm_none_eabi_gcc_no_64bit_multiplication () {
not grep __aeabi_lmul library/*.o not grep __aeabi_lmul library/*.o
} }
component_build_arm_clang_thumb () {
# ~ 30s
scripts/config.py baremetal
msg "build: clang thumb 2, make"
make clean
make CC="clang" CFLAGS='-std=c99 -Werror -Os --target=arm-linux-gnueabihf -march=armv7-m -mthumb' lib
# Some Thumb 1 asm is sensitive to optimisation level, so test both -O0 and -Os
msg "build: clang thumb 1 -O0, make"
make clean
make CC="clang" CFLAGS='-std=c99 -Werror -O0 --target=arm-linux-gnueabihf -mcpu=arm1136j-s -mthumb' lib
msg "build: clang thumb 1 -Os, make"
make clean
make CC="clang" CFLAGS='-std=c99 -Werror -Os --target=arm-linux-gnueabihf -mcpu=arm1136j-s -mthumb' lib
}
component_build_armcc () { component_build_armcc () {
msg "build: ARM Compiler 5" msg "build: ARM Compiler 5"
scripts/config.py baremetal scripts/config.py baremetal
@ -3918,7 +3937,7 @@ component_build_armcc () {
make clean make clean
# Compile with -O1 since some Arm inline assembly is disabled for -O0. # Compile mostly with -O1 since some Arm inline assembly is disabled for -O0.
# ARM Compiler 6 - Target ARMv7-A # ARM Compiler 6 - Target ARMv7-A
armc6_build_test "-O1 --target=arm-arm-none-eabi -march=armv7-a" armc6_build_test "-O1 --target=arm-arm-none-eabi -march=armv7-a"
@ -3937,6 +3956,12 @@ component_build_armcc () {
# ARM Compiler 6 - Target ARMv8.2-A - AArch64 # ARM Compiler 6 - Target ARMv8.2-A - AArch64
armc6_build_test "-O1 --target=aarch64-arm-none-eabi -march=armv8.2-a+crypto" armc6_build_test "-O1 --target=aarch64-arm-none-eabi -march=armv8.2-a+crypto"
# ARM Compiler 6 - Target Cortex-M0 - no optimisation
armc6_build_test "-O0 --target=arm-arm-none-eabi -mcpu=cortex-m0"
# ARM Compiler 6 - Target Cortex-M0
armc6_build_test "-Os --target=arm-arm-none-eabi -mcpu=cortex-m0"
} }
support_build_armcc () { support_build_armcc () {
armc5_cc="$ARMC5_BIN_DIR/armcc" armc5_cc="$ARMC5_BIN_DIR/armcc"