mirror/lwip
1
0
Fork 0
mirror of https://github.com/lwip-tcpip/lwip.git synced 2025-04-15 23:42:33 +00:00
Code Issues Packages Projects Releases Wiki Activity

Documentation - "Common pitfalls": Add some words about buffer alignment

Browse Source
This commit is contained in:
Dirk Ziegelmeier 2018-01-16 10:59:42 +01:00
parent 2fd83c9d2e
commit 72fc4a6ca5
1 changed files with 8 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
doc/doxygen/main_page.h
View File

@ -167,8 +167,8 @@
* These macros cannot be used in an interrupt context!
* Note the OS must correctly handle priority inversion for this.
*
* Cache issues
* ============
* Cache / DMA issues
* ==================
*
* DMA-capable ethernet hardware and zero-copy RX
* ----------------------------------------------
@ -182,6 +182,12 @@
* Also keep in mind the user application may also write into pbufs,
* so it is generally a bug not to flush the data cache before handing
* a buffer to DMA hardware.
*
* DMA-capable ethernet hardware and cacheline alignment
* -----------------------------------------------------
* Nice description about DMA capable hardware and buffer handling:
* http://www.pebblebay.com/a-guide-to-using-direct-memory-access-in-embedded-systems-part-two/
* Read especially sections "Cache coherency" and "Buffer alignment".
*/
/**