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Improve cache handling notes from my last commit some more
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@ -166,7 +166,7 @@
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* Note the OS must correctly handle priority inversion for this.
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*
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* Cache issues
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* ========================================
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* ============
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*
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* DMA-capable ethernet hardware and zero-copy RX
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* ----------------------------------------------
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@ -177,6 +177,9 @@
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* DMA ethernet hardware for the next telegram to be received.
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* See http://lwip.100.n7.nabble.com/in-place-overwriting-of-payload-via-static-quot-tcphdr-quot-pointer-td31434.html
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* for a more detailed explanation.
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* Also keep in mind the user application may also write into pbufs,
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* so it is generally a bug not to flush the data cache before handing
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* a buffer to DMA hardware.
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*/
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/**
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