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Improve cache handling notes from my last commit some more

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Dirk Ziegelmeier 2017-12-24 13:07:35 +01:00
parent 8f6b876ef9
commit 27ca731242
1 changed files with 4 additions and 1 deletions
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5
doc/doxygen/main_page.h
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@ -166,7 +166,7 @@
* Note the OS must correctly handle priority inversion for this. * Note the OS must correctly handle priority inversion for this.
* *
* Cache issues * Cache issues
* ======================================== * ============
* *
* DMA-capable ethernet hardware and zero-copy RX * DMA-capable ethernet hardware and zero-copy RX
* ---------------------------------------------- * ----------------------------------------------
@ -177,6 +177,9 @@
* DMA ethernet hardware for the next telegram to be received. * DMA ethernet hardware for the next telegram to be received.
* See http://lwip.100.n7.nabble.com/in-place-overwriting-of-payload-via-static-quot-tcphdr-quot-pointer-td31434.html * See http://lwip.100.n7.nabble.com/in-place-overwriting-of-payload-via-static-quot-tcphdr-quot-pointer-td31434.html
* for a more detailed explanation. * for a more detailed explanation.
* Also keep in mind the user application may also write into pbufs,
* so it is generally a bug not to flush the data cache before handing
* a buffer to DMA hardware.
*/ */
/** /**