1
0
mirror of https://github.com/CTCaer/hekate.git synced 2024-12-27 12:16:43 +00:00
hekate/bdk/mem
CTCaer fb31cb2926 bdk: ccplex: add no rst vector lock & powergating
Allow not locking the reset vectors and launch a new payload after powergating ccplex.
2024-03-13 01:37:52 +02:00
..
emc.h sdram: acquire per chip mrr info 2024-02-12 04:08:39 +02:00
heap.c
heap.h bdk: mem: improve emc MRR reading 2022-10-11 03:51:12 +03:00
mc_t210.h bdk: mem: improve emc MRR reading 2022-10-11 03:51:12 +03:00
mc.c bdk: mc: remove some redundant carveout cfg 2024-01-07 12:33:29 +02:00
mc.h
minerva.c bdk: sdram: adjust sdmmc1 la for l4t 2024-02-21 10:50:15 +02:00
minerva.h bdk: minerva: add custom option in table 2024-02-16 15:51:02 +02:00
mtc_table.h bdk: minerva: add custom option in table 2024-02-16 15:51:02 +02:00
sdram_config_t210b01.inl bdk: update copyright year 2024-01-07 12:38:10 +02:00
sdram_config.inl bdk: dram: add FPGA code for 3rd gen micron 2024-02-16 15:54:22 +02:00
sdram_param_t210.h
sdram_param_t210b01.h bdk: sdram: refactor patching offsets 2023-12-27 21:04:04 +02:00
sdram.c sdram: acquire per chip mrr info 2024-02-12 04:08:39 +02:00
sdram.h bdk: dram: add FPGA code for 3rd gen micron 2024-02-16 15:54:22 +02:00
smmu.c bdk: ccplex: add no rst vector lock & powergating 2024-03-13 01:37:52 +02:00
smmu.h