mirror of
https://github.com/CTCaer/hekate.git
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127 lines
3.4 KiB
C
127 lines
3.4 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _SDMMC_DRIVER_H_
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#define _SDMMC_DRIVER_H_
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#include "../utils/types.h"
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#include "sdmmc_t210.h"
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/*! SDMMC controller IDs. */
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#define SDMMC_1 0
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#define SDMMC_2 1
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#define SDMMC_3 2
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#define SDMMC_4 3
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/*! SDMMC power types. */
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#define SDMMC_POWER_OFF 0
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#define SDMMC_POWER_1_8 1
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#define SDMMC_POWER_3_3 2
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/*! SDMMC bus widths. */
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#define SDMMC_BUS_WIDTH_1 0
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#define SDMMC_BUS_WIDTH_4 1
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#define SDMMC_BUS_WIDTH_8 2
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/*! SDMMC response types. */
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#define SDMMC_RSP_TYPE_0 0
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#define SDMMC_RSP_TYPE_1 1
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#define SDMMC_RSP_TYPE_2 2
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#define SDMMC_RSP_TYPE_3 3
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#define SDMMC_RSP_TYPE_4 4
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#define SDMMC_RSP_TYPE_5 5
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/*! SDMMC mask interrupt status. */
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#define SDMMC_MASKINT_MASKED 0
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#define SDMMC_MASKINT_NOERROR -1
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#define SDMMC_MASKINT_ERROR -2
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/*! SDMMC host control 2 */
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#define SDHCI_CTRL_UHS_MASK 0xFFF8
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#define SDHCI_CTRL_VDD_330 0xFFF7
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#define SDHCI_CTRL_VDD_180 8
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#define SDHCI_CTRL_EXEC_TUNING 0x40
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#define SDHCI_CTRL_TUNED_CLK 0x80
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#define SDHCI_HOST_VERSION_4_EN 0x1000
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#define SDHCI_ADDRESSING_64BIT_EN 0x2000
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#define SDHCI_CTRL_PRESET_VAL_EN 0x8000
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/*! SD bus speeds. */
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#define UHS_SDR12_BUS_SPEED 0
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#define HIGH_SPEED_BUS_SPEED 1
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#define UHS_SDR25_BUS_SPEED 1
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#define UHS_SDR50_BUS_SPEED 2
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#define UHS_SDR104_BUS_SPEED 3
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#define UHS_DDR50_BUS_SPEED 4
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#define HS400_BUS_SPEED 5
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/*! Helper for SWITCH command argument. */
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#define SDMMC_SWITCH(mode, index, value) (((mode) << 24) | ((index) << 16) | ((value) << 8))
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/*! SDMMC controller context. */
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typedef struct _sdmmc_t
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{
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t210_sdmmc_t *regs;
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u32 id;
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u32 divisor;
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u32 clock_stopped;
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int no_sd;
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int sd_clock_enabled;
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int venclkctl_set;
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u32 venclkctl_tap;
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u32 expected_rsp_type;
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u32 dma_addr_next;
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u32 rsp[4];
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u32 rsp3;
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} sdmmc_t;
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/*! SDMMC command. */
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typedef struct _sdmmc_cmd_t
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{
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u16 cmd;
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u32 arg;
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u32 rsp_type;
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u32 check_busy;
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} sdmmc_cmd_t;
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/*! SDMMC request. */
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typedef struct _sdmmc_req_t
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{
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void *buf;
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u32 blksize;
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u32 num_sectors;
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int is_write;
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int is_multi_block;
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int is_auto_cmd12;
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} sdmmc_req_t;
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int sdmmc_get_voltage(sdmmc_t *sdmmc);
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u32 sdmmc_get_bus_width(sdmmc_t *sdmmc);
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void sdmmc_set_bus_width(sdmmc_t *sdmmc, u32 bus_width);
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void sdmmc_get_venclkctl(sdmmc_t *sdmmc);
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int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type);
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void sdmmc_sd_clock_ctrl(sdmmc_t *sdmmc, int no_sd);
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int sdmmc_get_rsp(sdmmc_t *sdmmc, u32 *rsp, u32 size, u32 type);
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int sdmmc_config_tuning(sdmmc_t *sdmmc, u32 type, u32 cmd);
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int sdmmc_stop_transmission(sdmmc_t *sdmmc, u32 *rsp);
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int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int no_sd);
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void sdmmc_end(sdmmc_t *sdmmc);
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void sdmmc_init_cmd(sdmmc_cmd_t *cmdbuf, u16 cmd, u32 arg, u32 rsp_type, u32 check_busy);
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int sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *blkcnt_out);
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int sdmmc_enable_low_voltage(sdmmc_t *sdmmc);
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#endif
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