mirror of
https://github.com/CTCaer/hekate.git
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240 lines
6.1 KiB
C
240 lines
6.1 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2020 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include <soc/i2c.h>
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#include <utils/util.h>
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#define I2C_PACKET_PROT_I2C (1 << 4)
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#define I2C_HEADER_IE_ENABLE (1 << 17)
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#define I2C_HEADER_READ (1 << 19)
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#define I2C_CNFG (0x00 / 4)
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#define CMD1_WRITE (0 << 6)
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#define CMD1_READ (1 << 6)
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#define NORMAL_MODE_GO (1 << 9)
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#define PACKET_MODE_GO (1 << 10)
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#define NEW_MASTER_FSM (1 << 11)
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#define DEBOUNCE_CNT_4T (2 << 12)
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#define I2C_CMD_ADDR0 (0x04 / 4)
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#define ADDR0_WRITE 0
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#define ADDR0_READ 1
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#define I2C_CMD_DATA1 (0x0C / 4)
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#define I2C_CMD_DATA2 (0x10 / 4)
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#define I2C_STATUS (0x1C / 4)
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#define I2C_STATUS_NOACK (0xF << 0)
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#define I2C_STATUS_BUSY (1 << 8)
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#define I2C_TX_FIFO (0x50 / 4)
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#define I2C_RX_FIFO (0x54 / 4)
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#define I2C_FIFO_CONTROL (0x5C / 4)
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#define RX_FIFO_FLUSH (1 << 0)
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#define TX_FIFO_FLUSH (1 << 1)
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#define I2C_FIFO_STATUS (0x60 / 4)
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#define RX_FIFO_FULL_CNT (0xF << 0)
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#define TX_FIFO_EMPTY_CNT (0xF << 4)
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#define I2C_INT_EN (0x64 / 4)
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#define I2C_INT_STATUS (0x68 / 4)
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#define I2C_INT_SOURCE (0x70 / 4)
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#define RX_FIFO_DATA_REQ (1 << 0)
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#define TX_FIFO_DATA_REQ (1 << 1)
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#define ARB_LOST (1 << 2)
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#define NO_ACK (1 << 3)
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#define RX_FIFO_UNDER (1 << 4)
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#define TX_FIFO_OVER (1 << 5)
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#define ALL_PACKETS_COMPLETE (1 << 6)
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#define PACKET_COMPLETE (1 << 7)
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#define BUS_CLEAR_DONE (1 << 11)
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#define I2C_CLK_DIVISOR (0x6C / 4)
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#define I2C_BUS_CLEAR_CONFIG (0x84 / 4)
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#define BC_ENABLE (1 << 0)
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#define BC_TERMINATE (1 << 1)
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#define I2C_BUS_CLEAR_STATUS (0x88 / 4)
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#define I2C_CONFIG_LOAD (0x8C / 4)
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#define MSTR_CONFIG_LOAD (1 << 0)
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#define TIMEOUT_CONFIG_LOAD (1 << 2)
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static const u32 i2c_addrs[] = {
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0x7000C000, // I2C_1.
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0x7000C400, // I2C_2.
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0x7000C500, // I2C_3.
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0x7000C700, // I2C_4.
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0x7000D000, // I2C_5.
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0x7000D100 // I2C_6.
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};
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static void _i2c_load_cfg_wait(vu32 *base)
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{
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base[I2C_CONFIG_LOAD] = (1 << 5) | TIMEOUT_CONFIG_LOAD | MSTR_CONFIG_LOAD;
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for (u32 i = 0; i < 20; i++)
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{
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usleep(1);
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if (!(base[I2C_CONFIG_LOAD] & MSTR_CONFIG_LOAD))
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break;
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}
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}
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static int _i2c_send_single(u32 i2c_idx, u32 dev_addr, u8 *buf, u32 size)
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{
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if (size > 8)
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return 0;
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u32 tmp = 0;
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vu32 *base = (vu32 *)i2c_addrs[i2c_idx];
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// Set device address and send mode.
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base[I2C_CMD_ADDR0] = dev_addr << 1 | ADDR0_WRITE;
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if (size > 4)
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{
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memcpy(&tmp, buf, 4);
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base[I2C_CMD_DATA1] = tmp; //Set value.
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tmp = 0;
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memcpy(&tmp, buf + 4, size - 4);
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base[I2C_CMD_DATA2] = tmp;
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}
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else
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{
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memcpy(&tmp, buf, size);
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base[I2C_CMD_DATA1] = tmp; //Set value.
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}
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// Set size and send mode.
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base[I2C_CNFG] = ((size - 1) << 1) | DEBOUNCE_CNT_4T | NEW_MASTER_FSM | CMD1_WRITE;
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// Load configuration.
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_i2c_load_cfg_wait(base);
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// Initiate transaction on normal mode.
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base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFF9FF) | NORMAL_MODE_GO;
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u32 timeout = get_tmr_ms() + 100; // Actual for max 8 bytes at 100KHz is 0.74ms.
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while (base[I2C_STATUS] & I2C_STATUS_BUSY)
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{
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if (get_tmr_ms() > timeout)
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return 0;
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}
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if (base[I2C_STATUS] & I2C_STATUS_NOACK)
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return 0;
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return 1;
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}
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static int _i2c_recv_single(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr)
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{
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if (size > 8)
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return 0;
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vu32 *base = (vu32 *)i2c_addrs[i2c_idx];
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// Set device address and recv mode.
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base[I2C_CMD_ADDR0] = (dev_addr << 1) | ADDR0_READ;
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// Set size and recv mode.
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base[I2C_CNFG] = ((size - 1) << 1) | DEBOUNCE_CNT_4T | NEW_MASTER_FSM | CMD1_READ;
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// Load configuration.
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_i2c_load_cfg_wait(base);
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// Initiate transaction on normal mode.
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base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFF9FF) | NORMAL_MODE_GO;
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u32 timeout = get_tmr_ms() + 100; // Actual for max 8 bytes at 100KHz is 0.74ms.
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while (base[I2C_STATUS] & I2C_STATUS_BUSY)
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{
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if (get_tmr_ms() > timeout)
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return 0;
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}
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if (base[I2C_STATUS] & I2C_STATUS_NOACK)
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return 0;
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u32 tmp = base[I2C_CMD_DATA1]; // Get LS value.
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if (size > 4)
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{
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memcpy(buf, &tmp, 4);
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tmp = base[I2C_CMD_DATA2]; // Get MS value.
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memcpy(buf + 4, &tmp, size - 4);
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}
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else
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memcpy(buf, &tmp, size);
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return 1;
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}
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void i2c_init(u32 i2c_idx)
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{
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vu32 *base = (vu32 *)i2c_addrs[i2c_idx];
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base[I2C_CLK_DIVISOR] = (5 << 16) | 1; // SF mode Div: 6, HS mode div: 2.
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base[I2C_BUS_CLEAR_CONFIG] = (9 << 16) | BC_TERMINATE | BC_ENABLE;
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// Load configuration.
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_i2c_load_cfg_wait(base);
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for (u32 i = 0; i < 10; i++)
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{
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usleep(20000);
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if (base[I2C_INT_STATUS] & BUS_CLEAR_DONE)
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break;
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}
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(vu32)base[I2C_BUS_CLEAR_STATUS];
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base[I2C_INT_STATUS] = base[I2C_INT_STATUS];
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}
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int i2c_recv_buf(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr)
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{
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return _i2c_recv_single(i2c_idx, buf, size, dev_addr);
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}
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int i2c_send_buf_small(u32 i2c_idx, u32 dev_addr, u32 reg, u8 *buf, u32 size)
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{
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u8 tmp[4];
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if (size > 7)
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return 0;
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tmp[0] = reg;
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memcpy(tmp + 1, buf, size);
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return _i2c_send_single(i2c_idx, dev_addr, tmp, size + 1);
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}
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int i2c_recv_buf_small(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr, u32 reg)
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{
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int res = _i2c_send_single(i2c_idx, dev_addr, (u8 *)®, 1);
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if (res)
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res = _i2c_recv_single(i2c_idx, buf, size, dev_addr);
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return res;
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}
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int i2c_send_byte(u32 i2c_idx, u32 dev_addr, u32 reg, u8 val)
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{
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return i2c_send_buf_small(i2c_idx, dev_addr, reg, &val, 1);
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}
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u8 i2c_recv_byte(u32 i2c_idx, u32 dev_addr, u32 reg)
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{
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u8 tmp = 0;
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i2c_recv_buf_small(&tmp, 1, i2c_idx, dev_addr, reg);
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return tmp;
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}
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