mirror of
https://github.com/CTCaer/hekate.git
synced 2024-12-27 03:15:21 +00:00
273 lines
6.6 KiB
C
273 lines
6.6 KiB
C
/*
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* Copyright (c) 2019-2021 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include "hos.h"
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#include "fss.h"
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#include "sept.h"
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#include "../config.h"
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#include <display/di.h>
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#include <ianos/ianos.h>
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#include <libs/fatfs/ff.h>
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#include <mem/heap.h>
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#include <soc/hw_init.h>
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#include <soc/pmc.h>
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#include <soc/t210.h>
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#include "../storage/emummc.h"
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#include "../storage/nx_emmc.h"
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#include <storage/nx_sd.h>
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#include <storage/sdmmc.h>
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#include <utils/btn.h>
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#include <utils/types.h>
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#include <gfx_utils.h>
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#define RELOC_META_OFF 0x7C
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#define PATCHED_RELOC_SZ 0x94
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#define WB_RST_ADDR 0x40010ED0
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#define WB_RST_SIZE 0x30
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u8 warmboot_reboot[] = {
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0x14, 0x00, 0x9F, 0xE5, // LDR R0, =0x7000E450
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0x01, 0x10, 0xB0, 0xE3, // MOVS R1, #1
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0x00, 0x10, 0x80, 0xE5, // STR R1, [R0]
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0x0C, 0x00, 0x9F, 0xE5, // LDR R0, =0x7000E400
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0x10, 0x10, 0xB0, 0xE3, // MOVS R1, #0x10
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0x00, 0x10, 0x80, 0xE5, // STR R1, [R0]
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0xFE, 0xFF, 0xFF, 0xEA, // LOOP
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0x50, 0xE4, 0x00, 0x70, // #0x7000E450
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0x00, 0xE4, 0x00, 0x70 // #0x7000E400
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};
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#define SEPT_PRI_ADDR 0x4003F000
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#define SEPT_PRI_ENTRY 0x40010340
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#define SEPT_PK1T_ADDR 0xC0400000
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#define SEPT_TCSZ_ADDR (SEPT_PK1T_ADDR - 0x4)
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#define SEPT_STG1_ADDR (SEPT_PK1T_ADDR + 0x2E100)
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#define SEPT_STG2_ADDR (SEPT_PK1T_ADDR + 0x60E0)
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#define SEPT_PKG_SZ (0x2F100 + WB_RST_SIZE)
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extern boot_cfg_t b_cfg;
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extern hekate_config h_cfg;
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extern const volatile ipl_ver_meta_t ipl_ver;
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extern bool is_ipl_updated(void *buf);
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extern void reloc_patcher(u32 payload_dst, u32 payload_src, u32 payload_size);
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void check_sept(ini_sec_t *cfg_sec)
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{
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if (h_cfg.t210b01)
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{
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h_cfg.sept_run = true;
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return;
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}
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hos_eks_get();
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// Check if non-hekate payload is used for sept and restore it.
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if (h_cfg.sept_run)
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{
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if (!f_stat("sept/payload.bak", NULL))
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{
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f_unlink("sept/payload.bin");
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f_rename("sept/payload.bak", "sept/payload.bin");
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}
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return;
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}
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u8 *pkg1 = (u8 *)calloc(1, 0x40000);
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int res = emummc_storage_init_mmc();
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if (res)
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{
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if (res == 2)
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EPRINTF("Failed to init eMMC.");
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else
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EPRINTF("Failed to init emuMMC.");
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goto out_free;
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}
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emummc_storage_set_mmc_partition(EMMC_BOOT0);
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// Read package1.
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emummc_storage_read(0x100000 / NX_EMMC_BLOCKSIZE, 0x40000 / NX_EMMC_BLOCKSIZE, pkg1);
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const pkg1_id_t *pkg1_id = pkg1_identify(pkg1);
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if (!pkg1_id)
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{
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EPRINTF("Unknown pkg1 version.");
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goto out_free;
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}
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if (pkg1_id->kb >= KB_FIRMWARE_VERSION_700 && !h_cfg.sept_run)
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{
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u32 key_idx = 0;
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if (pkg1_id->kb >= KB_FIRMWARE_VERSION_810)
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key_idx = 1;
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if (h_cfg.eks && h_cfg.eks->enabled[key_idx] >= pkg1_id->kb)
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{
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h_cfg.sept_run = true;
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goto out_free;
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}
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u8 *bct_bldr = (u8 *)calloc(1, 512);
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sdmmc_storage_read(&emmc_storage, 0x2200 / NX_EMMC_BLOCKSIZE, 1, &bct_bldr);
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u32 bootloader_entrypoint = *(u32 *)&bct_bldr[0x144];
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free(bct_bldr);
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if (bootloader_entrypoint > SEPT_PRI_ENTRY)
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{
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gfx_con.mute = false;
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EPRINTF("Failed to run sept\n""Main BCT is improper!\nRun sept with proper BCT at least once\nto cache keys.");
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goto out_free;
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}
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sdmmc_storage_end(&emmc_storage);
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reboot_to_sept((u8 *)pkg1 + pkg1_id->tsec_off, pkg1_id->kb, cfg_sec);
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}
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out_free:
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free(pkg1);
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sdmmc_storage_end(&emmc_storage);
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}
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int reboot_to_sept(const u8 *tsec_fw, u32 kb, ini_sec_t *cfg_sec)
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{
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FIL fp;
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bool fss0_sept_used = false;
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// Copy warmboot reboot code and TSEC fw.
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u32 tsec_fw_size = 0x3000;
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if (kb > KB_FIRMWARE_VERSION_700)
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tsec_fw_size = 0x3300;
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memcpy((u8 *)(SEPT_PK1T_ADDR - WB_RST_SIZE), (u8 *)warmboot_reboot, sizeof(warmboot_reboot));
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memcpy((void *)SEPT_PK1T_ADDR, tsec_fw, tsec_fw_size);
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*(vu32 *)SEPT_TCSZ_ADDR = tsec_fw_size;
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if (cfg_sec)
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{
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fss0_sept_t sept_ctxt;
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sept_ctxt.kb = kb;
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sept_ctxt.cfg_sec = cfg_sec;
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sept_ctxt.sept_primary = (void *)SEPT_STG1_ADDR;
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sept_ctxt.sept_secondary = (void *)SEPT_STG2_ADDR;
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fss0_sept_used = load_sept_from_ffs0(&sept_ctxt);
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}
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if (!fss0_sept_used)
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{
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// Copy sept-primary.
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if (f_open(&fp, "sept/sept-primary.bin", FA_READ))
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goto error;
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if (f_read(&fp, (u8 *)SEPT_STG1_ADDR, f_size(&fp), NULL))
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{
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f_close(&fp);
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goto error;
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}
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f_close(&fp);
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// Copy sept-secondary.
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if (kb < KB_FIRMWARE_VERSION_810)
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{
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if (f_open(&fp, "sept/sept-secondary_00.enc", FA_READ))
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goto error;
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}
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else
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{
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if (f_open(&fp, "sept/sept-secondary_01.enc", FA_READ))
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goto error;
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}
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if (f_read(&fp, (u8 *)SEPT_STG2_ADDR, f_size(&fp), NULL))
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{
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f_close(&fp);
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goto error;
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}
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f_close(&fp);
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}
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b_cfg.boot_cfg |= (BOOT_CFG_AUTOBOOT_EN | BOOT_CFG_SEPT_RUN);
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bool update_sept_payload = true;
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if (!f_open(&fp, "sept/payload.bin", FA_READ | FA_WRITE))
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{
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ipl_ver_meta_t tmp_ver;
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f_lseek(&fp, PATCHED_RELOC_SZ + sizeof(boot_cfg_t));
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f_read(&fp, &tmp_ver, sizeof(ipl_ver_meta_t), NULL);
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if (tmp_ver.magic == ipl_ver.magic)
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{
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if (tmp_ver.version == ipl_ver.version)
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{
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// Save auto boot config to sept payload, if any.
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boot_cfg_t *tmp_cfg = malloc(sizeof(boot_cfg_t));
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memcpy(tmp_cfg, &b_cfg, sizeof(boot_cfg_t));
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f_lseek(&fp, PATCHED_RELOC_SZ);
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f_write(&fp, tmp_cfg, sizeof(boot_cfg_t), NULL);
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update_sept_payload = false;
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}
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f_close(&fp);
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}
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else
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{
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f_close(&fp);
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f_rename("sept/payload.bin", "sept/payload.bak"); // Backup foreign payload.
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}
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}
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if (update_sept_payload)
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{
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volatile reloc_meta_t *reloc = (reloc_meta_t *)(IPL_LOAD_ADDR + RELOC_META_OFF);
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f_mkdir("sept");
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f_open(&fp, "sept/payload.bin", FA_WRITE | FA_CREATE_ALWAYS);
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f_write(&fp, (u8 *)reloc->start, reloc->end - reloc->start, NULL);
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f_close(&fp);
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}
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sd_end();
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u32 pk1t_sept = SEPT_PK1T_ADDR - (ALIGN(PATCHED_RELOC_SZ, 0x10) + WB_RST_SIZE);
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void (*sept)() = (void *)pk1t_sept;
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reloc_patcher(WB_RST_ADDR, pk1t_sept, SEPT_PKG_SZ);
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// Patch SDRAM init to perform an SVC immediately after second write.
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PMC(APBDEV_PMC_SCRATCH45) = 0x2E38DFFF;
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PMC(APBDEV_PMC_SCRATCH46) = 0x6001DC28;
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// Set SVC handler to jump to sept-primary in IRAM.
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PMC(APBDEV_PMC_SCRATCH33) = SEPT_PRI_ADDR;
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PMC(APBDEV_PMC_SCRATCH40) = 0x6000F208;
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hw_reinit_workaround(false, 0);
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(*sept)();
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error:
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gfx_con.mute = false;
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EPRINTF("Failed to run sept\n");
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btn_wait();
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return 0;
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} |