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hekate/modules/hekate_libsys_minerva
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CTCaer 05833bb38c minerva: update to v1.4 
- Correct Zqlatch period checks
- Update periodic training
- Simplify some logic
- Fix some mr13 values
- Separate EMC channel enums from macros
- Add extra reg flushes
- Fix tree margin comparison signedness
 By using incorrect signedness on tree margins the delta taps would always apply.
 By casting margins to integer it now properly checks if it should apply delta taps on the new trimmers.
 This fixes a bug that exists in every Nvidia emc dvfs code.
2021-05-11 10:23:08 +03:00
..
Makefile Add proper make prints for modules 2020-07-18 01:36:16 +03:00
mtc_mc_emc_regs.h minerva: update to v1.4 2021-05-11 10:23:08 +03:00
mtc_switch_tables.h mtc: Name sdram ids 2020-06-14 17:39:39 +03:00
mtc_table.h mtc: Refactor various types 2021-01-03 14:33:56 +02:00
mtc.h minerva: update to v1.4 2021-05-11 10:23:08 +03:00
README.md refactor: Remove all unwanted whitespace 2019-10-18 18:02:06 +03:00
sys_sdrammtc.c minerva: update to v1.4 2021-05-11 10:23:08 +03:00
types.h Minerva our DRAM trainer 2018-11-04 03:15:32 +02:00

README.md

Minerva Training Cell

Custom Nvidia Tegra X1 DRAM trainer.

For more, check Here.

Minerva Training Cell (c) 2018 CTCaer.

/* Pain... And suffering. */