1
0
mirror of https://github.com/CTCaer/hekate.git synced 2024-12-27 12:16:43 +00:00
hekate/bdk/mem
CTCaer 913cdee8e8 bdk: sdram: rename 3rd gen t210b01 hynix ram
Confirmed to be a Hynix H54G46CYRBX267 and not a H9HCNNNBKMMLXR-NEI
2023-12-25 03:02:11 +02:00
..
emc.h bdk: emc: add temp and feature reporting defines 2023-06-09 10:38:24 +03:00
heap.c bdk: whitespace refactor 2022-07-11 22:10:11 +03:00
heap.h bdk: mem: improve emc MRR reading 2022-10-11 03:51:12 +03:00
mc_t210.h bdk: mem: improve emc MRR reading 2022-10-11 03:51:12 +03:00
mc.c bdk: migrate timers/sleeps to timer driver 2022-06-27 10:22:19 +03:00
mc.h bdk: mc: always on ahb arbitration 2022-01-29 01:29:02 +02:00
minerva.c bdk: minerva: do not handle oc freq 2023-08-22 16:44:41 +03:00
minerva.h bdk: minerva: do not handle oc freq 2023-08-22 16:44:41 +03:00
mtc_table.h
sdram_config_t210b01.inl bdk: sdram: rename 3rd gen t210b01 hynix ram 2023-12-25 03:02:11 +02:00
sdram_config.inl bdk: sdram: rename 3rd gen t210b01 hynix ram 2023-12-25 03:02:11 +02:00
sdram_lp0_param_t210.h sc7: Add T210B01 SC7/LP0 (deep sleep) support 2020-06-26 19:00:30 +03:00
sdram_lp0_param_t210b01.h sc7: Add T210B01 SC7/LP0 (deep sleep) support 2020-06-26 19:00:30 +03:00
sdram_lp0.c sdram: fix building for embedded lp0 config 2021-09-17 23:17:56 +03:00
sdram_param_t210.h
sdram_param_t210b01.h
sdram.c bdk: sdram: rename 3rd gen t210b01 hynix ram 2023-12-25 03:02:11 +02:00
sdram.h bdk: sdram: rename 3rd gen t210b01 hynix ram 2023-12-25 03:02:11 +02:00
smmu.c bdk: whitespace refactor 2022-07-11 22:10:11 +03:00
smmu.h bdk: various functionality independent changes 2022-01-16 01:03:24 +02:00