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mirror of https://github.com/CTCaer/hekate.git synced 2024-11-20 05:11:42 +00:00
hekate/bdk/mem
CTCaer 7d3663616e bdk: sdram: name 2 of the new ram chips
Not actually validated, but educated guess, since all previous one were correct in the end.
New Micron still unknown, can be guessed but model doesn't exist in any public list.
2023-06-08 02:52:03 +03:00
..
emc.h
heap.c
heap.h bdk: mem: improve emc MRR reading 2022-10-11 03:51:12 +03:00
mc_t210.h
mc.c
mc.h
minerva.c
minerva.h
mtc_table.h Utilize hekate's BDK for hekate main and Nyx 2020-06-14 16:45:45 +03:00
sdram_config_t210b01.inl bdk: sdram: name 2 of the new ram chips 2023-06-08 02:52:03 +03:00
sdram_config.inl bdk: migrate timers/sleeps to timer driver 2022-06-27 10:22:19 +03:00
sdram_lp0_param_t210.h
sdram_lp0_param_t210b01.h
sdram_lp0.c
sdram_param_t210.h
sdram_param_t210b01.h
sdram.c bdk: sdram: name 2 of the new ram chips 2023-06-08 02:52:03 +03:00
sdram.h bdk: sdram: name 2 of the new ram chips 2023-06-08 02:52:03 +03:00
smmu.c
smmu.h