CTCaer 7d3663616e bdk: sdram: name 2 of the new ram chips ... Not actually validated, but educated guess, since all previous one were correct in the end. New Micron still unknown, can be guessed but model doesn't exist in any public list.		2023-06-08 02:52:03 +03:00
..
emc.h
heap.c	bdk: whitespace refactor	2022-07-11 22:10:11 +03:00
heap.h	bdk: mem: improve emc MRR reading	2022-10-11 03:51:12 +03:00
mc_t210.h	bdk: mem: improve emc MRR reading	2022-10-11 03:51:12 +03:00
mc.c
mc.h
minerva.c	bdk: mem: minerva: check table size in clock check	2023-06-08 02:45:34 +03:00
minerva.h	bdk: sdmmc: increase bw priority to SDMMC1 for L4T	2023-04-06 17:30:01 +03:00
mtc_table.h
sdram_config_t210b01.inl	bdk: sdram: name 2 of the new ram chips	2023-06-08 02:52:03 +03:00
sdram_config.inl
sdram_lp0_param_t210.h
sdram_lp0_param_t210b01.h
sdram_lp0.c
sdram_param_t210.h
sdram_param_t210b01.h
sdram.c	bdk: sdram: name 2 of the new ram chips	2023-06-08 02:52:03 +03:00
sdram.h	bdk: sdram: name 2 of the new ram chips	2023-06-08 02:52:03 +03:00
smmu.c	bdk: whitespace refactor	2022-07-11 22:10:11 +03:00
smmu.h