mirror of
https://github.com/CTCaer/hekate.git
synced 2024-11-20 14:19:13 +00:00
5e8eb1c57a
This will fix everything that uses a timer (or sleep). Without this any function like eMMC/SD read/write/verify, TSEC/SE, etc can break when the time reaches the max value of the u32 microsecond timer (71minutes). This fixes every possible breakage, including backup and restore (read/write/verify errors) that takes a lot of time. The new max before a timer reset is now 48 days (the old one was 71 minutes)
128 lines
3.5 KiB
C
Executable File
128 lines
3.5 KiB
C
Executable File
/*
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* Copyright (c) 2018 naehrwert
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cluster.h"
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#include "i2c.h"
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#include "clock.h"
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#include "util.h"
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#include "pmc.h"
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#include "t210.h"
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#include "max77620.h"
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void _cluster_enable_power()
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{
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u8 tmp = i2c_recv_byte(I2C_5, 0x3C, MAX77620_REG_AME_GPIO);
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i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_AME_GPIO, tmp & 0xDF);
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i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_GPIO5, 0x09);
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//Enable cores power.
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i2c_send_byte(I2C_5, 0x1B, 0x2, 0x20);
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i2c_send_byte(I2C_5, 0x1B, 0x3, 0x8D);
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i2c_send_byte(I2C_5, 0x1B, 0x0, 0xB7);
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i2c_send_byte(I2C_5, 0x1B, 0x1, 0xB7);
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}
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int _cluster_pmc_enable_partition(u32 part, u32 toggle)
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{
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//Check if the partition has already been turned on.
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if (PMC(APBDEV_PMC_PWRGATE_STATUS) & part)
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return 1;
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u32 i = 5001;
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while (PMC(APBDEV_PMC_PWRGATE_TOGGLE) & 0x100)
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{
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usleep(1);
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i--;
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if (i < 1)
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return 0;
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}
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PMC(APBDEV_PMC_PWRGATE_TOGGLE) = toggle | 0x100;
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i = 5001;
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while (i > 0)
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{
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if (PMC(APBDEV_PMC_PWRGATE_STATUS) & part)
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break;
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usleep(1);
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i--;
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}
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return 1;
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}
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void cluster_boot_cpu0(u32 entry)
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{
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//Set ACTIVE_CLUSER to FAST.
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FLOW_CTLR(FLOW_CTLR_BPMP_CLUSTER_CONTROL) &= 0xFFFFFFFE;
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_cluster_enable_power();
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if (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x40000000))
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{
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CLOCK(CLK_RST_CONTROLLER_PLLX_MISC_3) &= 0xFFFFFFF7;
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usleep(2);
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CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x80404E02;
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CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x404E02;
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CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) = (CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) & 0xFFFBFFFF) | 0x40000;
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CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x40404E02;
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}
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while (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x8000000))
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;
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//Configure MSELECT source and enable clock.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) & 0x1FFFFF00) | 6;
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) & 0xFFFFFFF7) | 8;
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//Configure initial CPU clock frequency and enable clock.
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CLOCK(CLK_RST_CONTROLLER_CCLK_BURST_POLICY) = 0x20008888;
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CLOCK(CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER) = 0x80000000;
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = 1;
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clock_enable_coresight();
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//CAR2PMC_CPU_ACK_WIDTH should be set to 0.
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CLOCK(CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2) &= 0xFFFFF000;
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//Enable CPU rail.
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_cluster_pmc_enable_partition(1, 0);
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//Enable cluster 0 non-CPU.
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_cluster_pmc_enable_partition(0x8000, 15);
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//Enable CE0.
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_cluster_pmc_enable_partition(0x4000, 14);
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//Request and wait for RAM repair.
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FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) = 1;
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while (!(FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) & 2))
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;
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EXCP_VEC(0x100) = 0;
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//Set reset vector.
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SB(SB_AA64_RESET_LOW) = entry | 1;
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SB(SB_AA64_RESET_HIGH) = 0;
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//Non-secure reset vector write disable.
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SB(SB_CSR) = 2;
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(void)SB(SB_CSR);
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//Clear MSELECT reset.
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CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_V) &= 0xFFFFFFF7;
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//Clear NONCPU reset.
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CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = 0x20000000;
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//Clear CPU{0,1,2,3} POR and CORE, CX0, L2, and DBG reset.
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CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = 0x411F000F;
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}
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