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mirror of https://github.com/CTCaer/hekate.git synced 2024-11-05 11:27:09 +00:00
hekate/modules/hekate_libsys_minerva
CTCaer 6a74f6ed04 minerva: make is_pllmb and fsp automatic
No need to keep these values around.
Software will automatically check the proper registers to get status.
2022-01-16 01:43:16 +02:00
..
Makefile
mtc_mc_emc_regs.h minerva: update to v1.4 2021-05-11 10:23:08 +03:00
mtc_switch_tables.h
mtc_table.h
mtc.h minerva: name needs_training flags 2022-01-16 01:41:24 +02:00
README.md
sys_sdrammtc.c minerva: make is_pllmb and fsp automatic 2022-01-16 01:43:16 +02:00
types.h minerva: make is_pllmb and fsp automatic 2022-01-16 01:43:16 +02:00

Minerva Training Cell

Custom Nvidia Tegra X1 DRAM trainer.

For more, check Here.

Minerva Training Cell (c) 2018 CTCaer.

/* Pain... And suffering. */