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37de367fef
Additionally add info about new hynix chip and correct ids 3 and 5 on T210B01 based Switch.
127 lines
5.4 KiB
C
127 lines
5.4 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2020-2021 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _SDRAM_H_
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#define _SDRAM_H_
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#include <mem/emc.h>
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/*
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* Tegra X1/X1+ EMC/DRAM Bandwidth Chart:
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*
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* Note: BWbits T210 = Hz x ddr x bus width x channels = Hz x 2 x 32 x 2.
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* BWbits T210B01 = Hz x ddr x bus width x channels = Hz x 2 x 64 x 2.
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* Both assume that both sub-partitions are used and thus reaching max
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* bandwidth per channel. (T210: 2x16-bit, T210B01: 2x32-bit).
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* Retail Mariko use one sub-partition, in order to meet Erista perf.
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*
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* T210 T210B01
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* 40.8 MHz: 0.61 1.22 GiB/s
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* 68.0 MHz: 1.01 2.02 GiB/s
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* 102.0 MHz: 1.52 3.04 GiB/s
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* 204.0 MHz: 3.04 6.08 GiB/s <-- Tegra X1/X1+ Init/SC7 Frequency
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* 408.0 MHz: 6.08 12.16 GiB/s
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* 665.6 MHz: 9.92 19.84 GiB/s
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* 800.0 MHz: 11.92 23.84 GiB/s <-- Tegra X1/X1+ Nvidia OS Boot Frequency
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* 1065.6 MHz: 15.89 31.78 GiB/s
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* 1331.2 MHz: 19.84 39.68 GiB/s
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* 1600.0 MHz: 23.84 47.68 GiB/s <-- Tegra X1/X1+ HOS Max Frequency
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* 1862.4 MHz: 27.75 55.50 GiB/s <-- Tegra X1 Official Max Frequency
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* 2131.2 MHz: 31.76 63.52 GiB/s <-- Tegra X1+ Official Max Frequency
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*
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*/
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enum sdram_ids_erista
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{
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// LPDDR4 3200Mbps.
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LPDDR4_ICOSA_4GB_SAMSUNG_K4F6E304HB_MGCH = 0,
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LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE = 1,
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LPDDR4_ICOSA_4GB_MICRON_MT53B512M32D2NP_062_WT = 2, // WT:C.
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LPDDR4_COPPER_4GB_SAMSUNG_K4F6E304HB_MGCH = 3, // Changed to Iowa Hynix 4GB 1Y-A.
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LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH = 4,
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LPDDR4_COPPER_4GB_HYNIX_H9HCNNNBPUMLHR_NLE = 5, // Changed to Hoag Hynix 4GB 1Y-A.
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LPDDR4_COPPER_4GB_MICRON_MT53B512M32D2NP_062_WT = 6, // Changed to Aula Hynix 4GB 1Y-A.
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};
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enum sdram_ids_mariko
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{
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// LPDDR4X 4266Mbps.
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LPDDR4X_HOAG_4GB_HYNIX_H9HCNNNBKMMLXR_NEE = 3, // Replaced from Copper. Die-M. (1y-01).
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LPDDR4X_IOWA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE = 5, // Replaced from Copper. Die-M. (1y-01).
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LPDDR4X_AULA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE = 6, // Replaced from Copper. Die-M. (1y-01).
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// LPDDR4X 3733Mbps.
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LPDDR4X_IOWA_4GB_SAMSUNG_X1X2 = 7,
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LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AM_MGCJ = 8, // Die-M.
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LPDDR4X_IOWA_8GB_SAMSUNG_K4UBE3D4AM_MGCJ = 9, // Die-M.
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LPDDR4X_IOWA_4GB_HYNIX_H9HCNNNBKMMLHR_NME = 10, // Die-M.
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LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WTE = 11, // 4266Mbps. Die-E.
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LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AM_MGCJ = 12, // Die-M.
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LPDDR4X_HOAG_8GB_SAMSUNG_K4UBE3D4AM_MGCJ = 13, // Die-M.
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LPDDR4X_HOAG_4GB_HYNIX_H9HCNNNBKMMLHR_NME = 14, // Die-M.
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LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTE = 15, // 4266Mbps. Die-E.
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// LPDDR4X 4266Mbps.
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LPDDR4X_IOWA_4GB_SAMSUNG_Y = 16, // (Y01).
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LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AA_MGCL = 17, // Die-A. (1y-X03).
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LPDDR4X_IOWA_8GB_SAMSUNG_K4UBE3D4AA_MGCL = 18, // Die-A. (1y-X03).
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LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AA_MGCL = 19, // Die-A. (1y-X03).
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LPDDR4X_IOWA_4GB_SAMSUNG_1Z = 20, // 1z nm. 40% lower power usage. (1z-B01).
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LPDDR4X_HOAG_4GB_SAMSUNG_1Z = 21, // 1z nm. 40% lower power usage. (1z-B01).
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LPDDR4X_AULA_4GB_SAMSUNG_1Z = 22, // 1z nm. 40% lower power usage. (1z-B01).
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LPDDR4X_HOAG_8GB_SAMSUNG_K4UBE3D4AA_MGCL = 23, // Die-A. (1y-X03).
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LPDDR4X_AULA_4GB_SAMSUNG_K4U6E3S4AA_MGCL = 24, // Die-A. (1y-X03).
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LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WTF = 25, // 4266Mbps. Die-F. D9XRR. 10nm-class (1y-01).
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LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTF = 26, // 4266Mbps. Die-F. D9XRR. 10nm-class (1y-01).
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LPDDR4X_AULA_4GB_MICRON_MT53E512M32D2NP_046_WTF = 27, // 4266Mbps. Die-F. D9XRR. 10nm-class (1y-01).
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LPDDR4X_AULA_8GB_SAMSUNG_K4UBE3D4AA_MGCL = 28, // Die-A.
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};
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enum sdram_codes_mariko
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{
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LPDDR4X_NO_PATCH = 0,
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LPDDR4X_UNUSED = 0,
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// LPDDR4X_4GB_SAMSUNG_K4U6E3S4AM_MGCJ DRAM IDs: 08, 12.
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// LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLHR_NME DRAM IDs: 10, 14.
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LPDDR4X_4GB_SAMSUNG_X1X2 = 1, // DRAM IDs: 07.
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LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ = 2, // DRAM IDs: 09, 13.
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LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE = 3, // DRAM IDs: 11, 15.
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LPDDR4X_4GB_SAMSUNG_Y = 4, // DRAM IDs: 16.
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LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL = 5, // DRAM IDs: 17, 19, 24.
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LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL = 6, // DRAM IDs: 18, 23, 28.
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LPDDR4X_4GB_SAMSUNG_1Z = 7, // DRAM IDs: 20, 21, 22.
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LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF = 8, // DRAM IDs: 25, 26, 27.
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LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE = 9, // DRAM IDs: 03, 05, 06.
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};
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void sdram_init();
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void *sdram_get_params_patched();
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void *sdram_get_params_t210b01();
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void sdram_lp0_save_params(const void *params);
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emc_mr_data_t sdram_read_mrx(emc_mr_t mrx);
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#endif
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