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https://github.com/CTCaer/hekate.git
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185526d134
BDK will allow developers to use the full collection of drivers, with limited editing, if any, for making payloads for Nintendo Switch. Using a single source for everything will also help decoupling Switch specific code and easily port it to other Tegra X1/X1+ platforms. And maybe even to lower targets. Everything is now centrilized into bdk folder. Every module or project can utilize it by simply including it. This is just the start and it will continue to improve.
170 lines
3.6 KiB
C
170 lines
3.6 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "util.h"
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#include "../gfx/di.h"
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#include "../mem/heap.h"
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#include "../mem/minerva.h"
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#include "../power/max77620.h"
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#include "../rtc/max77620-rtc.h"
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#include "../soc/bpmp.h"
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#include "../soc/hw_init.h"
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#include "../soc/i2c.h"
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#include "../soc/pmc.h"
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#include "../soc/t210.h"
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#include "../storage/nx_sd.h"
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#define USE_RTC_TIMER
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extern volatile nyx_storage_t *nyx_str;
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u32 get_tmr_s()
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{
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return RTC(APBDEV_RTC_SECONDS);
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}
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u32 get_tmr_ms()
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{
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// The registers must be read with the following order:
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// RTC_MILLI_SECONDS (0x10) -> RTC_SHADOW_SECONDS (0xC)
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return (RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000));
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}
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u32 get_tmr_us()
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{
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return TMR(TIMERUS_CNTR_1US); //TIMERUS_CNTR_1US
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}
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void msleep(u32 ms)
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{
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#ifdef USE_RTC_TIMER
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u32 start = RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000);
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// Casting to u32 is important!
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while (((u32)(RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000)) - start) <= ms)
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;
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#else
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bpmp_msleep(ms);
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#endif
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}
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void usleep(u32 us)
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{
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#ifdef USE_RTC_TIMER
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u32 start = TMR(TIMERUS_CNTR_1US);
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// Check if timer is at upper limits and use BPMP sleep so it doesn't wake up immediately.
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if ((start + us) < start)
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bpmp_usleep(us);
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else
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while ((u32)(TMR(TIMERUS_CNTR_1US) - start) <= us) // Casting to u32 is important!
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;
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#else
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bpmp_usleep(us);
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#endif
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}
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void exec_cfg(u32 *base, const cfg_op_t *ops, u32 num_ops)
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{
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for(u32 i = 0; i < num_ops; i++)
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base[ops[i].off] = ops[i].val;
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}
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u32 crc32_calc(u32 crc, const u8 *buf, u32 len)
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{
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const u8 *p, *q;
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static u32 *table = NULL;
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// Calculate CRC table.
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if (!table)
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{
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table = calloc(256, sizeof(u32));
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for (u32 i = 0; i < 256; i++)
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{
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u32 rem = i;
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for (u32 j = 0; j < 8; j++)
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{
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if (rem & 1)
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{
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rem >>= 1;
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rem ^= 0xedb88320;
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}
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else
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rem >>= 1;
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}
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table[i] = rem;
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}
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}
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crc = ~crc;
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q = buf + len;
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for (p = buf; p < q; p++)
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{
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u8 oct = *p;
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crc = (crc >> 8) ^ table[(crc & 0xff) ^ oct];
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}
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return ~crc;
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}
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void panic(u32 val)
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{
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// Set panic code.
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PMC(APBDEV_PMC_SCRATCH200) = val;
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//PMC(APBDEV_PMC_CRYPTO_OP) = PMC_CRYPTO_OP_SE_DISABLE;
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TMR(TIMER_WDT4_UNLOCK_PATTERN) = TIMER_MAGIC_PTRN;
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TMR(TIMER_TMR9_TMR_PTV) = TIMER_EN | TIMER_PER_EN;
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TMR(TIMER_WDT4_CONFIG) = TIMER_SRC(9) | TIMER_PER(1) | TIMER_PMCRESET_EN;
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TMR(TIMER_WDT4_COMMAND) = TIMER_START_CNT;
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while (true)
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usleep(1);
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}
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void reboot_normal()
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{
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sd_end();
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reconfig_hw_workaround(false, 0);
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panic(0x21); // Bypass fuse programming in package1.
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}
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void reboot_rcm()
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{
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sd_end();
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reconfig_hw_workaround(false, 0);
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PMC(APBDEV_PMC_SCRATCH0) = PMC_SCRATCH0_MODE_RCM;
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PMC(APBDEV_PMC_CNTRL) |= PMC_CNTRL_MAIN_RST;
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while (true)
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bpmp_halt();
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}
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void power_off()
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{
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sd_end();
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reconfig_hw_workaround(false, 0);
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// Stop the alarm, in case we injected and powered off too fast.
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max77620_rtc_stop_alarm();
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, MAX77620_ONOFFCNFG1_PWR_OFF);
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while (true)
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bpmp_halt();
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}
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