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https://github.com/CTCaer/hekate.git
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185526d134
BDK will allow developers to use the full collection of drivers, with limited editing, if any, for making payloads for Nintendo Switch. Using a single source for everything will also help decoupling Switch specific code and easily port it to other Tegra X1/X1+ platforms. And maybe even to lower targets. Everything is now centrilized into bdk folder. Every module or project can utilize it by simply including it. This is just the start and it will continue to improve.
102 lines
3.4 KiB
C
102 lines
3.4 KiB
C
/*
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* Copyright (c) 2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _MEMORY_MAP_H_
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#define _MEMORY_MAP_H_
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//#define IPL_STACK_TOP 0x4003FF00
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/* --- BIT/BCT: 0x40000000 - 0x40003000 --- */
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/* --- IPL: 0x40008000 - 0x40028000 --- */
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#define IPL_LOAD_ADDR 0x40008000
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#define IPL_SZ_MAX 0x20000 // 128KB.
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//#define IRAM_LIB_ADDR 0x4002B000
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#define SDRAM_PARAMS_ADDR 0x40030000 // SDRAM extraction buffer during sdram init.
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#define CBFS_DRAM_EN_ADDR 0x4003e000 // u32.
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/* --- DRAM START --- */
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#define DRAM_START 0x80000000
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#define HOS_RSVD 0x1000000 // Do not write anything in this area.
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#define NYX_LOAD_ADDR 0x81000000
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#define NYX_SZ_MAX 0x1000000 // 16MB
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/* --- Gap: 0x82000000 - 0x82FFFFFF --- */
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/* Stack theoretical max: 33MB */
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#define IPL_STACK_TOP 0x83100000
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#define IPL_HEAP_START 0x84000000
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#define IPL_HEAP_SZ 0x20000000 // 512MB.
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/* --- Gap: 1040MB 0xA4000000 - 0xE4FFFFFF --- */
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// Virtual disk / Chainloader buffers.
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#define RAM_DISK_ADDR 0xA4000000
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#define RAM_DISK_SZ 0x41000000 // 1040MB.
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//#define DRAM_LIB_ADDR 0xE0000000
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/* --- Chnldr: 252MB 0xC03C0000 - 0xCFFFFFFF --- */ //! Only used when chainloading.
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// SDMMC DMA buffers 1
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#define SDMMC_UPPER_BUFFER 0xE5000000
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#define SDMMC_UP_BUF_SZ 0x8000000 // 128MB.
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// Nyx buffers.
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#define NYX_STORAGE_ADDR 0xED000000
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#define NYX_RES_ADDR 0xEE000000
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#define NYX_RES_SZ 0x1000000 // 16MB.
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// SDMMC DMA buffers 2
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#define SDXC_BUF_ALIGNED 0xEF000000
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#define MIXD_BUF_ALIGNED 0xF0000000
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#define EMMC_BUF_ALIGNED MIXD_BUF_ALIGNED
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#define SDMMC_DMA_BUF_SZ 0x1000000 // 16MB (4MB currently used).
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// Nyx LvGL buffers.
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#define NYX_LV_VDB_ADR 0xF1000000
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#define NYX_FB_SZ 0x384000 // 1280 x 720 x 4.
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#define NYX_LV_MEM_ADR 0xF1400000
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#define NYX_LV_MEM_SZ 0x6600000 // 70MB.
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// Framebuffer addresses.
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#define IPL_FB_ADDRESS 0xF5A00000
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#define IPL_FB_SZ 0x384000 // 720 x 1280 x 4.
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#define LOG_FB_ADDRESS 0xF5E00000
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#define LOG_FB_SZ 0x334000 // 1280 x 656 x 4.
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#define NYX_FB_ADDRESS 0xF6200000
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#define NYX_FB2_ADDRESS 0xF6600000
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#define NYX_FB_SZ 0x384000 // 1280 x 720 x 4.
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#define DRAM_MEM_HOLE_ADR 0xF6A00000
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#define DRAM_MEM_HOLE_SZ 0x8140000
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/* --- Hole: 129MB 0xF6A00000 - 0xFEB3FFFF --- */
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#define DRAM_START2 0xFEB40000
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// NX BIS driver sector cache.
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#define NX_BIS_CACHE_ADDR 0xFEE00000
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#define NX_BIS_CACHE_SZ 0x100000
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// USB buffers.
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#define USBD_ADDR 0xFEF00000
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#define USB_DESCRIPTOR_ADDR 0xFEF40000
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#define USB_EP_CONTROL_BUF_ADDR 0xFEF80000
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#define USB_EP_BULK_IN_BUF_ADDR 0xFF000000
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#define USB_EP_BULK_OUT_BUF_ADDR 0xFF800000
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#define USB_EP_BULK_OUT_MAX_XFER 0x800000
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// #define EXT_PAYLOAD_ADDR 0xC0000000
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// #define RCM_PAYLOAD_ADDR (EXT_PAYLOAD_ADDR + ALIGN(PATCHED_RELOC_SZ, 0x10))
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// #define COREBOOT_ADDR (0xD0000000 - rom_size)
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#endif
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