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mirror of https://github.com/CTCaer/hekate.git synced 2024-11-20 05:11:42 +00:00
Commit Graph

21 Commits

Author SHA1 Message Date
CTCaer
523c81f797 nyx: Add theme colors for highlight text 2020-04-30 04:04:24 +03:00
CTCaer
8c762c52e2 Various fixes and whitespace removal 2020-04-30 03:25:22 +03:00
CTCaer
08c81fe1f8 Move verification config to nyx config 2020-04-30 02:00:33 +03:00
CTCaer
034f680a8e sd fs: Move sd init/mount/helpers to their own object 2020-04-29 23:20:18 +03:00
CTCaer
5b0a0070c7 sdmmc v2: Refactor everything 2020-04-29 18:53:29 +03:00
CTCaer
0462f3b252 Add simple exception handling
This adds support for exception handling.
It should provide simple and fast reporting of crucial info and full restoration without powering off.
2020-04-27 09:56:19 +03:00
CTCaer
9c6931a17c Bugfixes
The fan driver change ensures power off in any situation where a chainload software re-enables the 5V regulator.
2020-03-21 22:28:50 +02:00
CTCaer
d50af46b03 chnldr: Support variable sizes of coreboot.rom 2020-03-21 22:18:40 +02:00
CTCaer
a664118fc7 r2p: Update r2p payload
2 modes:
- With updater2p; Forces the reboot to payload binary to be hekate
- Without; Checks if hekate and then if old
2019-12-12 00:13:32 +02:00
CTCaer
c6e92311f9 Add error printing for issues with libraries
It will now show erros for the following:
- Missing or old libsys_minerva.bso (DRAM training).
- Missing libsys_lp0.bso (LP0 sleep mode).
- Missing or old Nyx version
2019-12-11 11:22:11 +02:00
CTCaer
f256bd5909 Move all I/DRAM addresses into a memory map
Many addresses were moved around to pack the memory usage!
2019-12-08 02:23:03 +02:00
Kostas Missos
48c15a8fde nyx: Release the shackles 2019-12-07 20:16:38 +02:00
Kostas Missos
0b45a5a11a bpmp: Reduce freq to 589MHz
3 users had issues with 602MHz.
This will probably bring the SoC binning compatibility to 100%.

Additionally, make it easy to change default boost frequency.

The tiny loss in perf, will be mitigated in Nyx. (It's actually even faster)
2019-12-07 02:01:29 +02:00
CTCaer
641a57a4f6 hos/mtc: Add FSP WAR and boost HOS booting times
By implementing FSP WAR we can allow HOS to boot in 1600MHz and be able to switch frequency without hanging.
2019-12-04 21:59:58 +02:00
CTCaer
0b1eebefe1 Small refactor and bugfixes 2019-12-04 21:31:39 +02:00
Kostas Missos
7c42f72b8a refactor: Remove all unwanted whitespace 2019-10-18 18:02:06 +03:00
CTCaer
a8d529cf6a Refactoring and comment adding 2019-09-12 23:08:38 +03:00
CTCaer
02826dd9a6 sdmmc: Streamline power cycle wait for Sandisks U1 2019-08-28 02:39:43 +03:00
CTCaer
f622d57f6b utils: Fix ms timer accuracy
Additionally add BPMP delay timers for future use.
2019-08-28 01:33:38 +03:00
ctcaer@gmail.com
08b84384a6 Bugfixes and cleanup 2019-07-06 22:08:37 +03:00
ctcaer@gmail.com
c41f98039c [Nyx] Introducing hekate GUI, named Nyx!
Version 0.8.0.

Expect dragons!
2019-06-30 04:03:00 +03:00