9 Commits

Author	SHA1	Message	Date
CTCaer	20c4d6dba6	minerva: update copyright years	2022-01-20 13:22:39 +02:00
CTCaer	d1c0d464dc	minerva: name needs_training flags	2022-01-16 01:41:24 +02:00
CTCaer	339ce2d861	minerva: change some types and fix temp check ... Temperature error check for over temp compensation was wrong. It's still unused though, so it didn't matter.	2021-10-15 16:48:51 +03:00
CTCaer	05833bb38c	minerva: update to v1.4 ... - Correct Zqlatch period checks - Update periodic training - Simplify some logic - Fix some mr13 values - Separate EMC channel enums from macros - Add extra reg flushes - Fix tree margin comparison signedness By using incorrect signedness on tree margins the delta taps would always apply. By casting margins to integer it now properly checks if it should apply delta taps on the new trimmers. This fixes a bug that exists in every Nvidia emc dvfs code.	2021-05-11 10:23:08 +03:00
CTCaer	faf5651607	minerva: more accurate clock tree delays ... Additionally, do not restore source DPD ctrl when switching frequencies or training is not needed.	2021-04-11 09:50:06 +03:00
CTCaer	d0a73bdc72	sc7: Add T210B01 SC7/LP0 (deep sleep) support ... Note to future self: Almost a month passed and nothing changed, have fun cleaning that in the end...	2020-06-26 19:00:30 +03:00
CTCaer	84328aa676	minerva: Make use of new minerva ... - Training and switch is now faster - Compatibility checks: New Minerva does not allow old binaries. New binaries do not allow old Minerva - MTC table is now in a safe region - Periodic training period increased to every 250ms	2019-12-04 21:56:45 +02:00
Kostas Missos	cfef8b4f72	Update libminerva to v1.1	2018-11-10 13:30:17 +02:00
Kostas Missos	cae9044c17	Minerva our DRAM trainer ... Supports up to 1600MHz and periodic training. For more check here: https://github.com/CTCaer/minerva_tc	2018-11-04 03:15:32 +02:00