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sdmmc: Properly disable parent clock
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@ -352,12 +352,9 @@ static void _clock_disable_pllc4(u32 mask)
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if (pllc4_enabled & PLLC4_IN_USE)
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return;
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//FIXME: This causes issues with L4T/TWRP.
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return;
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// Disable PLLC4.
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CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) &= ~PLLCX_BASE_ENABLE;
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CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) |= PLLCX_BASE_REF_DIS | PLLC4_BASE_IDDQ;
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CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) |= PLLC4_BASE_IDDQ;
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pllc4_enabled = 0;
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}
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