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bdk: vic: ease stress to APB when enabling VIC clk
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@ -536,9 +536,15 @@ int vic_compose()
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int vic_init()
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{
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// Ease the stress to APB.
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bpmp_freq_t prev_fid = bpmp_clk_rate_set(BPMP_CLK_NORMAL);
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clock_enable_host1x();
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clock_enable_vic();
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// Restore sys clock.
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bpmp_clk_rate_set(prev_fid);
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// Load Fetch Control Engine microcode.
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for (u32 i = 0; i < sizeof(vic_fce_ucode) / sizeof(u32); i++)
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{
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