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bdk: use static where it should
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@ -45,7 +45,7 @@ typedef struct _opt_win_cal_t
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} opt_win_cal_t;
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// Nintendo Switch Icosa/Iowa Optical Window calibration.
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const opt_win_cal_t opt_win_cal_default[] = {
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static const opt_win_cal_t opt_win_cal_default[] = {
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{ 500, 5002, 7502 },
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{ 754, 2250, 2000 },
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{ 1029, 1999, 1667 },
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@ -54,14 +54,14 @@ const opt_win_cal_t opt_win_cal_default[] = {
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};
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// Nintendo Switch Aula Optical Window calibration.
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const opt_win_cal_t opt_win_cal_aula[] = {
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static const opt_win_cal_t opt_win_cal_aula[] = {
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{ 231, 9697, 30300 },
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{ 993, 3333, 2778 },
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{ 1478, 1621, 1053 },
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{ 7500, 81, 10 }
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};
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const u32 als_gain_idx_tbl[4] = { 1, 2, 64, 128 };
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static const u32 als_gain_idx_tbl[4] = { 1, 2, 64, 128 };
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void set_als_cfg(als_ctxt_t *als_ctxt, u8 gain, u8 cycle)
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{
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@ -536,8 +536,8 @@ static u8 _jc_hid_pkt_id_incr()
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static void _jc_send_hid_cmd(u8 uart, u8 subcmd, u8 *data, u16 size)
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{
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const u8 rumble_neutral[8] = { 0x00, 0x01, 0x40, 0x40, 0x00, 0x01, 0x40, 0x40 };
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const u8 rumble_init[8] = { 0xc2, 0xc8, 0x03, 0x72, 0xc2, 0xc8, 0x03, 0x72 };
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static const u8 rumble_neutral[8] = { 0x00, 0x01, 0x40, 0x40, 0x00, 0x01, 0x40, 0x40 };
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static const u8 rumble_init[8] = { 0xc2, 0xc8, 0x03, 0x72, 0xc2, 0xc8, 0x03, 0x72 };
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u8 temp[0x30] = {0};
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@ -118,7 +118,7 @@
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#define MMU_EN_READ BIT(2)
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#define MMU_EN_WRITE BIT(3)
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bpmp_mmu_entry_t mmu_entries[] =
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static const bpmp_mmu_entry_t mmu_entries[] =
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{
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{ DRAM_START, 0xFFFFFFFF, MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC | MMU_EN_CACHED, true },
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{ IRAM_BASE, 0x4003FFFF, MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC | MMU_EN_CACHED, true }
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@ -140,7 +140,7 @@ void bpmp_mmu_maintenance(u32 op, bool force)
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BPMP_CACHE_CTRL(BPMP_CACHE_INT_CLEAR) = BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT);
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}
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void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply)
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void bpmp_mmu_set_entry(int idx, const bpmp_mmu_entry_t *entry, bool apply)
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{
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if (idx > 31)
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return;
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@ -59,7 +59,7 @@ typedef enum
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#define BPMP_CLK_DEFAULT_BOOST BPMP_CLK_HYPER_BOOST
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void bpmp_mmu_maintenance(u32 op, bool force);
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void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply);
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void bpmp_mmu_set_entry(int idx, const bpmp_mmu_entry_t *entry, bool apply);
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void bpmp_mmu_enable();
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void bpmp_mmu_disable();
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void bpmp_clk_rate_relaxed(bool enable);
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@ -81,6 +81,7 @@
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#define CL_DVFS_BASE 0x70110000
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#define APE_BASE 0x702C0000
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#define AHUB_BASE 0x702D0000
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#define ADMAIF_BASE 0x702D0000
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#define AXBAR_BASE 0x702D0800
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#define I2S_BASE 0x702D1000
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#define ADMA_BASE 0x702E2000
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@ -275,7 +275,7 @@ reinit_try:
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// Disk IO failure! Reinit SD/EMMC to a lower speed.
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if (storage->sdmmc->id == SDMMC_1 || storage->sdmmc->id == SDMMC_4)
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{
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int res;
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int res = 0;
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if (storage->sdmmc->id == SDMMC_1)
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{
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2023 CTCaer
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* Copyright (c) 2018-2024 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -109,8 +109,8 @@ void sdmmc_save_tap_value(sdmmc_t *sdmmc)
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static int _sdmmc_config_tap_val(sdmmc_t *sdmmc, u32 type)
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{
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const u32 dqs_trim_val = 40; // 24 if HS533/HS667.
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const u8 tap_values_t210[4] = { 4, 0, 3, 0 };
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static const u32 dqs_trim_val = 40; // 24 if HS533/HS667.
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static const u8 tap_values_t210[4] = { 4, 0, 3, 0 };
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u32 tap_val = 0;
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@ -1366,8 +1366,8 @@ int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type)
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u16 divisor;
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u8 vref_sel = 7;
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const u8 trim_values_t210[4] = { 2, 8, 3, 8 };
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const u8 trim_values_t210b01[4] = { 14, 13, 15, 13 };
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static const u8 trim_values_t210[4] = { 2, 8, 3, 8 };
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static const u8 trim_values_t210b01[4] = { 14, 13, 15, 13 };
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const u8 *trim_values;
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if (id > SDMMC_4 || id == SDMMC_3)
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