mirror of
https://github.com/CTCaer/hekate.git
synced 2024-12-26 00:16:33 +00:00
bdk: uart: fix fifo clear
- Do not clear fifo for everything if not needed - Correct fifo clear checks
This commit is contained in:
parent
f2be59888b
commit
8bf3bee08b
@ -174,14 +174,14 @@ void uart_empty_fifo(u32 idx, u32 which)
|
|||||||
(void)uart->UART_SPR;
|
(void)uart->UART_SPR;
|
||||||
usleep(96);
|
usleep(96);
|
||||||
|
|
||||||
uart->UART_IIR_FCR = UART_IIR_FCR_EN_FIFO | UART_IIR_FCR_TX_CLR | UART_IIR_FCR_RX_CLR;
|
uart->UART_IIR_FCR = UART_IIR_FCR_EN_FIFO | which;
|
||||||
(void)uart->UART_SPR;
|
(void)uart->UART_SPR;
|
||||||
usleep(18);
|
usleep(18);
|
||||||
u32 tries = 0;
|
u32 tries = 0;
|
||||||
|
|
||||||
if (UART_IIR_FCR_TX_CLR & which)
|
if (UART_IIR_FCR_TX_CLR & which)
|
||||||
{
|
{
|
||||||
while (tries < 10 && uart->UART_LSR & UART_LSR_TMTY)
|
while (tries < 10 && !(uart->UART_LSR & UART_LSR_TMTY))
|
||||||
{
|
{
|
||||||
tries++;
|
tries++;
|
||||||
usleep(100);
|
usleep(100);
|
||||||
@ -191,7 +191,7 @@ void uart_empty_fifo(u32 idx, u32 which)
|
|||||||
|
|
||||||
if (UART_IIR_FCR_RX_CLR & which)
|
if (UART_IIR_FCR_RX_CLR & which)
|
||||||
{
|
{
|
||||||
while (tries < 10 && !uart->UART_LSR & UART_LSR_RDR)
|
while (tries < 10 && (uart->UART_LSR & UART_LSR_RDR))
|
||||||
{
|
{
|
||||||
tries++;
|
tries++;
|
||||||
usleep(100);
|
usleep(100);
|
||||||
|
Loading…
Reference in New Issue
Block a user