mirror of
https://github.com/CTCaer/hekate.git
synced 2024-07-08 05:38:47 +00:00
l4t: update loader to v6
- Move TZ parameters to a static address inside TZDRAM - Update fw rev for new ARC - Refactor context and parameters into a single struct
This commit is contained in:
CTCaer
parent
6c601ccaa5
commit
85cd26e305
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@ -35,10 +35,11 @@
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* 3: Arachne Register Cell v2. PTSA Rework support.
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* 4: Arachne Register Cell v3. DRAM OPT and DDR200 changes.
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* 5: Arachne Register Cell v4. DRAM FREQ and DDR200 changes.
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* 6: Arachne Register Cell v5. Signal quality and performance changes. TZ param changes.
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*/
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#define L4T_LOADER_API_REV 5
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#define L4T_FIRMWARE_REV 0x35524556 // REV5.
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#define L4T_LOADER_API_REV 6
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#define L4T_FIRMWARE_REV 0x36524556 // REV6.
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#ifdef DEBUG_UART_PORT
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#include <soc/uart.h>
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@ -52,16 +53,18 @@
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#endif
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#if CARVEOUT_NVDEC_TSEC_ENABLE
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#define TZ_SIZE SZ_8M
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#define TZDRAM_SIZE_CFG SZ_8M
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#else
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#define TZ_SIZE SZ_1M
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#define TZDRAM_SIZE_CFG SZ_1M
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#endif
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// TZDRAM addresses and sizes.
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#define TZDRAM_SIZE TZ_SIZE // Secure Element.
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#define TZDRAM_BASE (0xFFFFFFFF - TZDRAM_SIZE + 1) // 0xFFF00000 or 0xFF800000.
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#define TZDRAM_SIZE TZDRAM_SIZE_CFG // Secure Element.
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#define TZDRAM_BASE (0xFFFFFFFF - TZDRAM_SIZE + 1) // 0xFFF00000 or 0xFF800000.
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#define TZDRAM_COLD_ENTRY (TZDRAM_BASE)
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#define TZDRAM_WARM_ENTRY (TZDRAM_BASE + 0x200)
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#define TZ_PARAM_SIZE SZ_4K
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#define TZ_PARAM_BASE (0xFFFFFFFF - TZ_PARAM_SIZE + 1) // 0xFFFFF000.
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// Carveout sizes.
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#define CARVEOUT_NVDEC_SIZE SZ_1M
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@ -76,8 +79,14 @@
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#define SC7ENTRY_HDR_SIZE 0x400
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// Always start 1MB below TZDRAM for Secure Firmware or NVDEC.
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#define GEN_CARVEOUT_TOP (TZDRAM_BASE - SZ_1M)
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// NVDEC and SECFW bases.
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#define NVDFW_BASE GEN_CARVEOUT_TOP // 0xFF700000.
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#define SECFW_BASE GEN_CARVEOUT_TOP // 0xFFE00000.
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// Secure Elements addresses for T210.
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#define SECFW_BASE (TZDRAM_BASE - SZ_1M) // 0xFFE00000 or 0xFF700000.
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#define SC7ENTRY_HDR_BASE (SECFW_BASE + 0)
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#define SC7ENTRY_BASE (SECFW_BASE + SC7ENTRY_HDR_SIZE) // After header.
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#define SC7EXIT_BASE (SECFW_BASE + SZ_64K) // 64KB after SECFW_BASE.
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@ -214,7 +223,7 @@ typedef struct _bl_v1_params {
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u64 bl32_image_info;
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u64 bl33_ep_info;
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u64 bl33_image_info;
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} bl_v1_params_t;
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} bl31_v1_params_t;
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typedef struct _plat_params_from_bl2 {
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// TZDRAM.
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@ -243,7 +252,7 @@ typedef struct _plat_params_from_bl2 {
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u64 r2p_payload_base;
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u64 flags; // Platform flags.
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} plat_params_from_bl2_t;
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} bl31_plat_params_from_bl2_t;
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typedef struct _l4t_fw_t
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{
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@ -265,6 +274,10 @@ typedef struct _l4t_ctxt_t
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u32 sc7entry_size;
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emc_table_t *mtc_table;
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bl31_v1_params_t bl31_v1_params;
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bl31_plat_params_from_bl2_t bl31_plat_params;
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entry_point_info_t bl33_ep_info;
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} l4t_ctxt_t;
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#define DRAM_VDD2_OC_MIN_VOLTAGE 1050
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@ -483,7 +496,7 @@ static void _l4t_mc_config_carveout(bool t210b01)
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UPRINTF("TZD: TZDRAM Carveout: %08X - %08X\n", TZDRAM_BASE, TZDRAM_BASE - 1 + TZDRAM_SIZE);
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// Configure generalized security carveouts.
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u32 carveout_base = TZDRAM_BASE - SZ_1M; // Always leave space for Secure Firmware.
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u32 carveout_base = GEN_CARVEOUT_TOP;
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#if CARVEOUT_NVDEC_TSEC_ENABLE
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@ -549,8 +562,10 @@ static void _l4t_mc_config_carveout(bool t210b01)
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MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2) = 0;
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MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3) = 0;
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MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4) = 0;
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MC(MC_SECURITY_CARVEOUT1_CFG0) = SEC_CARVEOUT_CFG_RD_NS |
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SEC_CARVEOUT_CFG_WR_NS |
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MC(MC_SECURITY_CARVEOUT1_CFG0) = SEC_CARVEOUT_CFG_RD_NS |
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SEC_CARVEOUT_CFG_RD_SEC |
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SEC_CARVEOUT_CFG_WR_NS |
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SEC_CARVEOUT_CFG_WR_SEC |
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SEC_CARVEOUT_CFG_LOCKED;
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UPRINTF("GSC1: SECFW Carveout: %08X - %08X\n",
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MC(MC_SECURITY_CARVEOUT1_BOM), MC(MC_SECURITY_CARVEOUT1_BOM) + MC(MC_SECURITY_CARVEOUT1_SIZE_128KB) * SZ_128K);
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@ -910,7 +925,7 @@ static void _l4t_set_config(l4t_ctxt_t *ctxt, const ini_sec_t *ini_sec, int entr
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_l4t_bl33_cfg_set_key(bl33_env, "autoboot_list", val);
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val[0] = '0' + L4T_LOADER_API_REV;
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_l4t_bl33_cfg_set_key(bl33_env, "loader_rev", val);
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_l4t_bl33_cfg_set_key(bl33_env, "loader_rev", val);
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// Enable BL33 memory env import.
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*(u32 *)(BL33_ENV_MAGIC_OFFSET) = BL33_ENV_MAGIC;
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@ -923,25 +938,23 @@ static void _l4t_set_config(l4t_ctxt_t *ctxt, const ini_sec_t *ini_sec, int entr
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void launch_l4t(const ini_sec_t *ini_sec, int entry_idx, int is_list, bool t210b01)
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{
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l4t_ctxt_t ctxt = {0};
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bl_v1_params_t bl_v1_params = {0};
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plat_params_from_bl2_t plat_params = {0};
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entry_point_info_t bl33_ep_info = {0};
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l4t_ctxt_t *ctxt = (l4t_ctxt_t *)TZ_PARAM_BASE;
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memset(ctxt, 0, TZ_PARAM_SIZE);
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gfx_con_setpos(0, 0);
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// Parse config.
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_l4t_set_config(&ctxt, ini_sec, entry_idx, is_list, t210b01);
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_l4t_set_config(ctxt, ini_sec, entry_idx, is_list, t210b01);
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if (!ctxt.path)
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if (!ctxt->path)
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{
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_l4t_crit_error("Path missing", false);
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return;
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}
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// Get MTC table.
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ctxt.mtc_table = minerva_get_mtc_table();
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if (!t210b01 && !ctxt.mtc_table)
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ctxt->mtc_table = minerva_get_mtc_table();
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if (!t210b01 && !ctxt->mtc_table)
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{
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_l4t_crit_error("Minerva missing", true);
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return;
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@ -968,8 +981,8 @@ void launch_l4t(const ini_sec_t *ini_sec, int entry_idx, int is_list, bool t210b
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if (!t210b01)
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{
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// Load SC7-Entry firmware.
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ctxt.sc7entry_size = _l4t_sd_load(SC7ENTRY_FW);
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if (!ctxt.sc7entry_size)
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ctxt->sc7entry_size = _l4t_sd_load(SC7ENTRY_FW);
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if (!ctxt->sc7entry_size)
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{
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_l4t_crit_error("loading SC7-Entry", true);
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return;
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@ -1017,10 +1030,10 @@ void launch_l4t(const ini_sec_t *ini_sec, int entry_idx, int is_list, bool t210b
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mc_disable_ahb_redirect();
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// Enable debug port.
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if (ctxt.serial_port)
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if (ctxt->serial_port)
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{
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pinmux_config_uart(ctxt.serial_port - 1);
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clock_enable_uart(ctxt.serial_port - 1);
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pinmux_config_uart(ctxt->serial_port - 1);
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clock_enable_uart(ctxt->serial_port - 1);
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}
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// Restore UARTB/C TX pins to SPIO.
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@ -1032,7 +1045,7 @@ void launch_l4t(const ini_sec_t *ini_sec, int entry_idx, int is_list, bool t210b
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{
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// Defaults are for UARTA.
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char *bl33_serial_port = NULL;
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switch (ctxt.serial_port)
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switch (ctxt->serial_port)
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{
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case 0: // Disable.
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break;
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@ -1051,41 +1064,41 @@ void launch_l4t(const ini_sec_t *ini_sec, int entry_idx, int is_list, bool t210b
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{
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BL33_DTB_SET_STDOUT_PATH(bl33_serial_port);
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BL33_DTB_SET_STDERR_PATH(bl33_serial_port);
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BL33_DTB_SET_UART_STATUS(ctxt.serial_port);
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BL33_DTB_SET_UART_STATUS(ctxt->serial_port);
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}
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}
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// Set BL31 params.
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bl_v1_params.hdr.type = PARAM_BL31;
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bl_v1_params.hdr.version = VERSION_1;
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bl_v1_params.hdr.size = sizeof(bl_v1_params_t);
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bl_v1_params.hdr.attr = PARAM_EP_SECURE;
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bl_v1_params.bl33_ep_info = (u64)(u32)&bl33_ep_info;
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ctxt->bl31_v1_params.hdr.type = PARAM_BL31;
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ctxt->bl31_v1_params.hdr.version = VERSION_1;
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ctxt->bl31_v1_params.hdr.size = sizeof(bl31_v1_params_t);
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ctxt->bl31_v1_params.hdr.attr = PARAM_EP_SECURE;
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ctxt->bl31_v1_params.bl33_ep_info = (u64)(u32)&ctxt->bl33_ep_info;
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// Set BL33 params.
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bl33_ep_info.hdr.type = PARAM_EP;
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bl33_ep_info.hdr.version = VERSION_1;
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bl33_ep_info.hdr.size = sizeof(entry_point_info_t);
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bl33_ep_info.hdr.attr = PARAM_EP_NON_SECURE;
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bl33_ep_info.pc = BL33_LOAD_BASE;
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bl33_ep_info.spsr = SPSR_EL2T;
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ctxt->bl33_ep_info.hdr.type = PARAM_EP;
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ctxt->bl33_ep_info.hdr.version = VERSION_1;
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ctxt->bl33_ep_info.hdr.size = sizeof(entry_point_info_t);
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ctxt->bl33_ep_info.hdr.attr = PARAM_EP_NON_SECURE;
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ctxt->bl33_ep_info.pc = BL33_LOAD_BASE;
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ctxt->bl33_ep_info.spsr = SPSR_EL2T;
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// Set Platform parameters.
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plat_params.tzdram_base = TZDRAM_BASE;
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plat_params.tzdram_size = TZDRAM_SIZE;
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ctxt->bl31_plat_params.tzdram_base = TZDRAM_BASE;
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ctxt->bl31_plat_params.tzdram_size = TZDRAM_SIZE;
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#if DEBUG_LOG_ATF
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plat_params.uart_id = ctxt.serial_port;
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ctxt->bl31_plat_params.uart_id = ctxt->serial_port;
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#endif
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if (!t210b01)
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{
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// Set SC7-Entry fw parameters. For now BPMP-FW is not used on T210.
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plat_params.sc7entry_fw_base = SC7ENTRY_HDR_BASE;
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plat_params.sc7entry_fw_size = ALIGN(ctxt.sc7entry_size + SC7ENTRY_HDR_SIZE, SZ_PAGE);
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ctxt->bl31_plat_params.sc7entry_fw_base = SC7ENTRY_HDR_BASE;
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ctxt->bl31_plat_params.sc7entry_fw_size = ALIGN(ctxt->sc7entry_size + SC7ENTRY_HDR_SIZE, SZ_PAGE);
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}
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// Enable below features.
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plat_params.enable_extra_features = BL31_EXTRA_FEATURES_ENABLE;
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ctxt->bl31_plat_params.enable_extra_features = BL31_EXTRA_FEATURES_ENABLE;
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if (!t210b01)
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{
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@ -1095,37 +1108,37 @@ void launch_l4t(const ini_sec_t *ini_sec, int entry_idx, int is_list, bool t210b
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memset((u8 *)R2P_PAYLOAD_BASE + 0x94, 0, sizeof(boot_cfg_t)); // Clear Boot Config Storage.
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// Set R2P payload fw parameters.
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plat_params.r2p_payload_base = R2P_PAYLOAD_BASE;
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plat_params.r2p_payload_size = ALIGN(reloc->end - reloc->start, SZ_PAGE);
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ctxt->bl31_plat_params.r2p_payload_base = R2P_PAYLOAD_BASE;
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ctxt->bl31_plat_params.r2p_payload_size = ALIGN(reloc->end - reloc->start, SZ_PAGE);
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}
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// Set PMC access security. NS is mandatory for T210B01.
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plat_params.flags = FLAGS_PMC_NON_SECURE; // Unsecure it unconditionally to reduce SMC calls to a minimum.
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ctxt->bl31_plat_params.flags = FLAGS_PMC_NON_SECURE; // Unsecure it unconditionally to reduce SMC calls to a minimum.
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// Lift SC7 placement restrictions. Disables TZDRAM increased carveout too.
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plat_params.flags |= FLAGS_SC7_NO_BASE_RESTRICTION;
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ctxt->bl31_plat_params.flags |= FLAGS_SC7_NO_BASE_RESTRICTION;
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// Prepare EMC table.
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if (ctxt.mtc_table)
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if (ctxt->mtc_table)
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{
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// Set DRAM voltage.
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if (ctxt.ram_oc_vdd2)
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max7762x_regulator_set_voltage(REGULATOR_SD1, ctxt.ram_oc_vdd2 * 1000);
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if (ctxt->ram_oc_vdd2)
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max7762x_regulator_set_voltage(REGULATOR_SD1, ctxt->ram_oc_vdd2 * 1000);
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// Train the rest of the table, apply FSP WAR, set RAM to 800 MHz.
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minerva_prep_boot_l4t(ctxt.ram_oc_freq, ctxt.ram_oc_opt);
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minerva_prep_boot_l4t(ctxt->ram_oc_freq, ctxt->ram_oc_opt);
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// Set emc table parameters and copy it.
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int table_entries = minerva_get_mtc_table_entries();
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plat_params.emc_table_base = MTCTABLE_BASE;
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plat_params.emc_table_size = sizeof(emc_table_t) * table_entries;
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memcpy((u32 *)MTCTABLE_BASE, ctxt.mtc_table, sizeof(emc_table_t) * table_entries);
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ctxt->bl31_plat_params.emc_table_base = MTCTABLE_BASE;
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ctxt->bl31_plat_params.emc_table_size = sizeof(emc_table_t) * table_entries;
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memcpy((u32 *)MTCTABLE_BASE, ctxt->mtc_table, sizeof(emc_table_t) * table_entries);
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}
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// Set and enable IRAM based BL31 config.
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PMC(APBDEV_PMC_SECURE_SCRATCH112) = PMC(APBDEV_PMC_SECURE_SCRATCH108);
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PMC(APBDEV_PMC_SECURE_SCRATCH114) = PMC(APBDEV_PMC_SECURE_SCRATCH109);
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PMC(APBDEV_PMC_SECURE_SCRATCH108) = (u32)&bl_v1_params;
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PMC(APBDEV_PMC_SECURE_SCRATCH109) = (u32)&plat_params;
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PMC(APBDEV_PMC_SECURE_SCRATCH108) = (u32)&ctxt->bl31_v1_params;
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PMC(APBDEV_PMC_SECURE_SCRATCH109) = (u32)&ctxt->bl31_plat_params;
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PMC(APBDEV_PMC_SECURE_SCRATCH110) = BL31_IRAM_PARAMS;
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// Set panel model.
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@ -1145,7 +1158,7 @@ void launch_l4t(const ini_sec_t *ini_sec, int entry_idx, int is_list, bool t210b
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// Set BPMP-FW parameters.
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if (t210b01)
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_l4t_bpmpfw_b01_config(&ctxt);
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_l4t_bpmpfw_b01_config(ctxt);
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// Set carveouts and save them to PMC for SC7 Exit.
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_l4t_mc_config_carveout(t210b01);
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