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bdk: bpmp: add and use bpmp_clk_rate_relaxed
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@ -1,7 +1,7 @@
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/*
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* VIC driver for Tegra X1
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*
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* Copyright (c) 2018-2023 CTCaer
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* Copyright (c) 2018-2024 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -539,14 +539,8 @@ int vic_compose()
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int vic_init()
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{
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// Ease the stress to APB.
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bpmp_freq_t prev_fid = bpmp_clk_rate_set(BPMP_CLK_NORMAL);
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clock_enable_vic();
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// Restore sys clock.
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bpmp_clk_rate_set(prev_fid);
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// Load Fetch Control Engine microcode.
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for (u32 i = 0; i < sizeof(vic_fce_ucode) / sizeof(u32); i++)
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{
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@ -1215,17 +1215,11 @@ void jc_init_hw()
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pinmux_config_uart(UART_B);
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pinmux_config_uart(UART_C);
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// Ease the stress to APB.
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bpmp_freq_t prev_fid = bpmp_clk_rate_set(BPMP_CLK_NORMAL);
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// Enable UART B and C clocks.
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if (!jc_gamepad.sio_mode)
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clock_enable_uart(UART_B);
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clock_enable_uart(UART_C);
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// Restore OC.
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bpmp_clk_rate_set(prev_fid);
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jc_init_done = true;
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#endif
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}
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@ -75,7 +75,7 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
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void *ptb;
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bpmp_mmu_disable();
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bpmp_freq_t prev_fid = bpmp_clk_rate_set(BPMP_CLK_NORMAL);
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bpmp_clk_rate_relaxed(true);
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// Enable clocks.
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clock_enable_tsec();
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@ -305,7 +305,7 @@ out:
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clock_disable_sor_safe();
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clock_disable_tsec();
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bpmp_mmu_enable();
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bpmp_clk_rate_set(prev_fid);
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bpmp_clk_rate_relaxed(false);
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#ifdef BDK_MC_ENABLE_AHB_REDIRECT
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// Re-enable AHB aperture.
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@ -1,7 +1,7 @@
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/*
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* BPMP-Lite Cache/MMU and Frequency driver for Tegra X1
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*
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* Copyright (c) 2019-2023 CTCaer
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* Copyright (c) 2019-2024 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -200,10 +200,44 @@ void bpmp_mmu_disable()
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BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) = 0;
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}
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/*
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* CLK_RST_CONTROLLER_SCLK_BURST_POLICY:
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* 0 = CLKM
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* 1 = PLLC_OUT1
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* 2 = PLLC4_OUT3
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* 3 = PLLP_OUT0
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* 4 = PLLP_OUT2
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* 5 = PLLC4_OUT1
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* 6 = CLK_S
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* 7 = PLLC4_OUT2
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*/
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bpmp_freq_t bpmp_fid_current = BPMP_CLK_NORMAL;
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void bpmp_clk_rate_relaxed(bool enable)
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{
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// This is a glitch-free way to reduce the SCLK timings.
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if (enable)
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{
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// Restore to PLLP source during PLLC configuration.
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003330; // PLLP_OUT.
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usleep(100); // Wait a bit for clock source change.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // PCLK = HCLK / (2 + 1). HCLK == SCLK.
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}
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else if (bpmp_fid_current)
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{
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// Restore to PLLC_OUT1.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 3; // PCLK = HCLK / (3 + 1). HCLK == SCLK.
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003310; // PLLC_OUT1 and CLKM for idle.
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usleep(100); // Wait a bit for clock source change.
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}
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}
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// APB clock affects RTC, PWM, MEMFETCH, APE, USB, SOR PWM,
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// I2C host, DC/DSI/DISP. UART gives extra stress.
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// 92: 100% success ratio. 93-94: 595-602MHz has 99% success ratio. 95: 608MHz less.
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const u8 pll_divn[] = {
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static const u8 pll_divn[] = {
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0, // BPMP_CLK_NORMAL: 408MHz 0% - 136MHz APB.
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85, // BPMP_CLK_HIGH_BOOST: 544MHz 33% - 136MHz APB.
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88, // BPMP_CLK_HIGH2_BOOST: 563MHz 38% - 141MHz APB.
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@ -213,8 +247,6 @@ const u8 pll_divn[] = {
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//95 // BPMP_CLK_DEV_BOOST: 608MHz 49% - 152MHz APB.
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};
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bpmp_freq_t bpmp_fid_current = BPMP_CLK_NORMAL;
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void bpmp_clk_rate_get()
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{
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bool clk_src_is_pllp = ((CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) >> 4) & 7) == 3;
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@ -237,45 +269,35 @@ void bpmp_clk_rate_get()
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}
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}
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bpmp_freq_t bpmp_clk_rate_set(bpmp_freq_t fid)
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void bpmp_clk_rate_set(bpmp_freq_t fid)
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{
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bpmp_freq_t prev_fid = bpmp_fid_current;
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if (fid > (BPMP_CLK_MAX - 1))
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fid = BPMP_CLK_MAX - 1;
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if (prev_fid == fid)
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return prev_fid;
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if (bpmp_fid_current == fid)
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return;
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bpmp_fid_current = fid;
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if (fid)
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{
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if (prev_fid)
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{
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// Restore to PLLP source during PLLC configuration.
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; // PLLP_OUT.
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msleep(1); // Wait a bit for clock source change.
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}
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// Use default SCLK / HCLK / PCLK clocks.
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bpmp_clk_rate_relaxed(true);
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// Configure and enable PLLC.
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clock_enable_pllc(pll_divn[fid]);
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// Set SCLK / HCLK / PCLK.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 3; // PCLK = HCLK / (3 + 1). HCLK == SCLK.
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003310; // PLLC_OUT1 for active and CLKM for idle.
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// Set new source and SCLK / HCLK / PCLK dividers.
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bpmp_clk_rate_relaxed(false);
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}
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else
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{
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003330; // PLLP_OUT for active and CLKM for idle.
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msleep(1); // Wait a bit for clock source change.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // PCLK = HCLK / (2 + 1). HCLK == SCLK.
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// Use default SCLK / HCLK / PCLK clocks.
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bpmp_clk_rate_relaxed(true);
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// Disable PLLC to save power.
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clock_disable_pllc();
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}
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bpmp_fid_current = fid;
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// Return old fid in case of temporary swap.
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return prev_fid;
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}
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// The following functions halt BPMP to reduce power while sleeping.
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@ -1,7 +1,7 @@
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/*
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* BPMP-Lite Cache/MMU and Frequency driver for Tegra X1
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*
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* Copyright (c) 2019-2023 CTCaer
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* Copyright (c) 2019-2024 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -62,8 +62,9 @@ void bpmp_mmu_maintenance(u32 op, bool force);
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void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply);
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void bpmp_mmu_enable();
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void bpmp_mmu_disable();
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void bpmp_clk_rate_relaxed(bool enable);
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void bpmp_clk_rate_get();
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bpmp_freq_t bpmp_clk_rate_set(bpmp_freq_t fid);
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void bpmp_clk_rate_set(bpmp_freq_t fid);
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void bpmp_usleep(u32 us);
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void bpmp_msleep(u32 ms);
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void bpmp_halt();
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@ -15,6 +15,7 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <soc/bpmp.h>
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#include <soc/clock.h>
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#include <soc/hw_init.h>
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#include <soc/pmc.h>
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@ -153,7 +154,13 @@ void clock_enable_fuse(bool enable)
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void clock_enable_uart(u32 idx)
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{
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// Ease the stress to APB.
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bpmp_clk_rate_relaxed(true);
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clock_enable(&_clock_uart[idx]);
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// Restore OC.
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bpmp_clk_rate_relaxed(false);
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}
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void clock_disable_uart(u32 idx)
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@ -247,7 +254,13 @@ void clock_disable_nvjpg()
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void clock_enable_vic()
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{
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// Ease the stress to APB.
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bpmp_clk_rate_relaxed(true);
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clock_enable(&_clock_vic);
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// Restore sys clock.
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bpmp_clk_rate_relaxed(false);
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}
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void clock_disable_vic()
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@ -323,7 +336,13 @@ void clock_disable_coresight()
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void clock_enable_pwm()
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{
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// Ease the stress to APB.
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bpmp_clk_rate_relaxed(true);
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clock_enable(&_clock_pwm);
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// Restore OC.
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bpmp_clk_rate_relaxed(false);
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}
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void clock_disable_pwm()
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@ -464,10 +483,10 @@ void clock_enable_pllc(u32 divn)
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;
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// Disable PLLC_OUT1, enable reset and set div to 1.5.
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) = BIT(8);
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) = 1 << 8;
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// Enable PLLC_OUT1 and bring it out of reset.
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) |= (PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR);
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CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) |= PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR;
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msleep(1); // Wait a bit for PLL to stabilize.
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}
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@ -1,7 +1,7 @@
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/*
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* Fan driver for Nintendo Switch
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*
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* Copyright (c) 2018-2023 CTCaer
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* Copyright (c) 2018-2024 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -49,16 +49,8 @@ void set_fan_duty(u32 duty)
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// Enable PWM if disabled.
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if (fuse_read_hw_type() == FUSE_NX_HW_TYPE_AULA)
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{
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// Ease the stress to APB.
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bpmp_freq_t prev_fid = bpmp_clk_rate_set(BPMP_CLK_NORMAL);
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clock_enable_pwm();
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// Restore OC.
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bpmp_clk_rate_set(prev_fid);
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}
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PWM(PWM_CONTROLLER_PWM_CSR_1) = PWM_CSR_EN | (0x100 << 16); // Max PWM to disable fan.
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PINMUX_AUX(PINMUX_AUX_LCD_GPIO2) = 1; // Set source to PWM1.
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