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l4t: bump api to 7
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@ -36,10 +36,11 @@
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* 4: Arachne Register Cell v3. DRAM OPT and DDR200 changes.
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* 5: Arachne Register Cell v4. DRAM FREQ and DDR200 changes.
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* 6: Arachne Register Cell v5. Signal quality and performance changes. TZ param changes.
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* 7: Arachne Register Cell v6. Decouple of rd/wr latencies.
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*/
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#define L4T_LOADER_API_REV 6
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#define L4T_FIRMWARE_REV 0x36524556 // REV6.
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#define L4T_LOADER_API_REV 7
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#define L4T_FIRMWARE_REV 0x37524556 // REV7.
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#ifdef DEBUG_UART_PORT
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#include <soc/uart.h>
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