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uart: use proper interrupt decoding

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This commit is contained in:
CTCaer 2021-03-17 08:51:49 +02:00
parent e8cf85bd65
commit 513f77a2ad
3 changed files with 18 additions and 2 deletions
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2
bdk/input/joycon.c
View File

@ -463,7 +463,7 @@ static void jc_rcv_pkt(joycon_ctxt_t *jc)
// Check if device stopped sending data.
u32 uart_irq = uart_get_IIR(jc->uart);
if ((uart_irq & 0x8) != 0x8)
if (uart_irq != UART_IIR_REDI)
return;
u32 len = uart_recv(jc->uart, (u8 *)jc->buf, 0x100);

7
bdk/soc/uart.c
View File

@ -122,7 +122,12 @@ u32 uart_get_IIR(u32 idx)
{
uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
return uart->UART_IIR_FCR;
u32 iir = uart->UART_IIR_FCR & UART_IIR_INT_MASK;
if (iir & UART_IIR_NO_INT)
return 0;
else
return ((iir >> 1) + 1); // Return encoded interrupt.
}
void uart_set_IIR(u32 idx)

11
bdk/soc/uart.h
View File

@ -54,6 +54,17 @@
#define UART_IIR_FCR_RX_CLR 0x2
#define UART_IIR_FCR_EN_FIFO 0x1
#define UART_IIR_NO_INT BIT(0)
#define UART_IIR_INT_MASK 0xF
/* Custom returned interrupt results. Actual interrupts are -1 */
#define UART_IIR_NOI 0 // No interrupt.
#define UART_IIR_MSI 1 // Modem status interrupt.
#define UART_IIR_THRI 2 // Transmitter holding register empty.
#define UART_IIR_RDI 3 // Receiver data interrupt.
#define UART_IIR_ERROR 4 // Overrun Error, Parity Error, Framing Error, Break.
#define UART_IIR_REDI 5 // Receiver end of data interrupt.
#define UART_IIR_RDTI 7 // Receiver data timeout interrupt.
#define UART_MCR_RTS 0x2
#define UART_MCR_DTR 0x1