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bdk: display: small refactor
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c321d3508c
commit
4c5cc6d567
@ -384,7 +384,7 @@ void display_init()
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_DISP1);
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = BIT(CLK_X_UART_FST_MIPI_CAL);
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL) = CLK_SRC_DIV(6); // Set PLLP_OUT3 and div 6 (17MHz).
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL) = CLK_SRC_DIV(6); // Set PLLP_OUT3 and div 6 (68MHz).
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_SET) = BIT(CLK_W_DSIA_LP);
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP) = CLK_SRC_DIV(6); // Set PLLP_OUT and div 6 (68MHz).
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@ -437,16 +437,16 @@ void display_init()
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reg_write_array((u32 *)DISPLAY_A_BASE, _di_dc_setup_win_config, ARRAY_SIZE(_di_dc_setup_win_config));
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// Setup dsi init sequence packets.
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reg_write_array((u32 *)DSI_BASE, _di_dsi_init_config0, ARRAY_SIZE(_di_dsi_init_config0));
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reg_write_array((u32 *)DSI_BASE, _di_dsi_seq_pkt_reset_config0, ARRAY_SIZE(_di_dsi_seq_pkt_reset_config0));
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DSI(_DSIREG(tegra_t210 ? DSI_INIT_SEQ_DATA_15 : DSI_INIT_SEQ_DATA_15_B01)) = 0;
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reg_write_array((u32 *)DSI_BASE, _di_dsi_init_config1, ARRAY_SIZE(_di_dsi_init_config1));
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reg_write_array((u32 *)DSI_BASE, _di_dsi_seq_pkt_reset_config1, ARRAY_SIZE(_di_dsi_seq_pkt_reset_config1));
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// Reset pad trimmers for T210B01.
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if (!tegra_t210)
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reg_write_array((u32 *)DSI_BASE, _di_dsi_init_pads_t210b01, ARRAY_SIZE(_di_dsi_init_pads_t210b01));
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// Setup init sequence packets, timings and power on DSI.
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reg_write_array((u32 *)DSI_BASE, _di_dsi_init_config2, ARRAY_SIZE(_di_dsi_init_config2));
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// Setup init seq packet lengths, timings and power on DSI.
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reg_write_array((u32 *)DSI_BASE, _di_dsi_init_config, ARRAY_SIZE(_di_dsi_init_config));
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usleep(10000);
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// Enable LCD Reset.
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@ -557,13 +557,13 @@ void display_init()
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clock_enable_plld(1, 24, false, tegra_t210);
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// Finalize DSI init packet sequence configuration.
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reg_write_array((u32 *)DSI_BASE, _di_dsi_init_seq_pkt_final_config, ARRAY_SIZE(_di_dsi_init_seq_pkt_final_config));
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reg_write_array((u32 *)DSI_BASE, _di_dsi_seq_pkt_video_non_burst_no_eot_config, ARRAY_SIZE(_di_dsi_seq_pkt_video_non_burst_no_eot_config));
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// Set 1-by-1 pixel/clock and pixel clock to 234 / 3 = 78 MHz. For 60 Hz refresh rate.
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DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4); // 4: div3.
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// Set DSI mode.
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reg_write_array((u32 *)DSI_BASE, _di_dsi_mode_config, ARRAY_SIZE(_di_dsi_mode_config));
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// Set DSI mode to HOST.
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reg_write_array((u32 *)DSI_BASE, _di_dsi_host_mode_config, ARRAY_SIZE(_di_dsi_host_mode_config));
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usleep(10000);
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/*
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@ -734,6 +734,7 @@ static void _display_panel_and_hw_end(bool no_panel_deinit)
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case PANEL_AUO_A062TAN01:
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reg_write_array((u32 *)DSI_BASE, _di_dsi_panel_deinit_config_auo, ARRAY_SIZE(_di_dsi_panel_deinit_config_auo));
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usleep(5000);
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break;
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case PANEL_INL_2J055IA_27A:
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@ -64,7 +64,7 @@ static const reg_cfg_t _di_dc_setup_win_config[] = {
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};
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// DSI Init config.
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static const reg_cfg_t _di_dsi_init_config0[] = {
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static const reg_cfg_t _di_dsi_seq_pkt_reset_config0[] = {
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{DSI_WR_DATA, 0},
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{DSI_INT_ENABLE, 0},
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{DSI_INT_STATUS, 0},
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@ -74,7 +74,7 @@ static const reg_cfg_t _di_dsi_init_config0[] = {
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{DSI_INIT_SEQ_DATA_2, 0},
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{DSI_INIT_SEQ_DATA_3, 0}
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};
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static const reg_cfg_t _di_dsi_init_config1[] = {
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static const reg_cfg_t _di_dsi_seq_pkt_reset_config1[] = {
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{DSI_DCS_CMDS, 0},
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{DSI_PKT_SEQ_0_LO, 0},
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{DSI_PKT_SEQ_1_LO, 0},
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@ -99,37 +99,47 @@ static const reg_cfg_t _di_dsi_init_pads_t210b01[] = {
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{DSI_PAD_CONTROL_6_B01, 0},
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{DSI_PAD_CONTROL_7_B01, 0}
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};
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static const reg_cfg_t _di_dsi_init_config2[] = {
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static const reg_cfg_t _di_dsi_init_config[] = {
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{DSI_PAD_CONTROL_CD, 0},
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{DSI_SOL_DELAY, 24},
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{DSI_MAX_THRESHOLD, 480},
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{DSI_TRIGGER, 0},
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{DSI_INIT_SEQ_CONTROL, 0},
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{DSI_PKT_LEN_0_1, 0},
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{DSI_PKT_LEN_2_3, 0},
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{DSI_PKT_LEN_4_5, 0},
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{DSI_PKT_LEN_6_7, 0},
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{DSI_PAD_CONTROL_1, 0},
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/* DSI PHY timings */
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{DSI_PHY_TIMING_0, 0x6070603},
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{DSI_PHY_TIMING_1, 0x40A0E05},
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{DSI_PHY_TIMING_2, 0x30109},
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{DSI_BTA_TIMING, 0x190A14},
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/* DSI timeout */
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{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
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{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)},
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{DSI_TO_TALLY, 0},
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{DSI_PAD_CONTROL_0, DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0)}, // Power up.
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{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
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{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
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{DSI_POWER_CONTROL, 0},
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{DSI_POWER_CONTROL, 0},
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{DSI_PAD_CONTROL_1, 0},
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/* DSI PHY timings */
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{DSI_PHY_TIMING_0, 0x6070603},
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{DSI_PHY_TIMING_1, 0x40A0E05},
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{DSI_PHY_TIMING_2, 0x30118},
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{DSI_BTA_TIMING, 0x190A14},
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/* DSI timeout */
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{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
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{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)},
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{DSI_TO_TALLY, 0},
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{DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
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{DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE},
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{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
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@ -188,15 +198,19 @@ static const reg_cfg_t _di_dsi_panel_init_config_jdi[] = {
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};
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// DSI packet config.
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static const reg_cfg_t _di_dsi_init_seq_pkt_final_config[] = {
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static const reg_cfg_t _di_dsi_seq_pkt_video_non_burst_no_eot_config[] = {
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{DSI_PAD_CONTROL_1, 0},
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/* DSI PHY timings */
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{DSI_PHY_TIMING_0, 0x6070603},
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{DSI_PHY_TIMING_1, 0x40A0E05},
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{DSI_PHY_TIMING_2, 0x30172},
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{DSI_BTA_TIMING, 0x190A14},
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/* DSI timeout */
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{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)},
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{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)},
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{DSI_TO_TALLY, 0},
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{DSI_PKT_SEQ_0_LO, 0x40000208},
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{DSI_PKT_SEQ_2_LO, 0x40000308},
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{DSI_PKT_SEQ_4_LO, 0x40000308},
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@ -213,7 +227,7 @@ static const reg_cfg_t _di_dsi_init_seq_pkt_final_config[] = {
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};
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// DSI mode config.
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static const reg_cfg_t _di_dsi_mode_config[] = {
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static const reg_cfg_t _di_dsi_host_mode_config[] = {
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{DSI_TRIGGER, 0},
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{DSI_CONTROL, 0},
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{DSI_SOL_DELAY, 6},
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@ -304,6 +318,7 @@ static const reg_cfg_t _di_dc_video_enable_config[] = {
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{DC_CMD_GENERAL_INCR_SYNCPT, SYNCPT_GENERAL_COND(COND_REG_WR_SAFE) | SYNCPT_GENERAL_INDX(1)},
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{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
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{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
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{DC_DISP_DISP_CLOCK_CONTROL, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4)}, // 4: div3.
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};
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@ -334,13 +349,17 @@ static const reg_cfg_t _di_dc_video_disable_config[] = {
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static const reg_cfg_t _di_dsi_timing_deinit_config[] = {
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{DSI_POWER_CONTROL, 0},
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{DSI_PAD_CONTROL_1, 0},
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/* DSI PHY timings */
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{DSI_PHY_TIMING_0, 0x6070603},
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{DSI_PHY_TIMING_1, 0x40A0E05},
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{DSI_PHY_TIMING_2, 0x30118},
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{DSI_BTA_TIMING, 0x190A14},
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/* DSI timeout */
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{DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)},
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{DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)},
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{DSI_TO_TALLY, 0},
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{DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC},
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{DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE},
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{DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE},
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