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https://github.com/CTCaer/hekate.git
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hwinit: add seamless display (L4T Linux/Android)
Initial support is for coreboot based preloading.
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@ -88,6 +88,7 @@ static void _config_oscillators()
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3.
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}
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// The uart is skipped for Copper, Hoag and Calcio. Used in Icosa, Iowa and Aula.
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static void _config_gpios(bool nx_hoag)
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{
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// Clamp inputs when tristated.
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@ -420,7 +421,7 @@ void hw_init()
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bpmp_mmu_enable();
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}
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void hw_reinit_workaround(bool coreboot, u32 magic)
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void hw_reinit_workaround(bool coreboot, u32 bl_magic)
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{
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// Disable BPMP max clock.
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bpmp_clk_rate_set(BPMP_CLK_NORMAL);
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@ -462,11 +463,22 @@ void hw_reinit_workaround(bool coreboot, u32 magic)
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PMC(APBDEV_PMC_NO_IOPOWER) &= ~(PMC_NO_IOPOWER_SDMMC1_IO_EN);
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}
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// Power off display.
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display_end();
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// Seamless display or display power off.
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switch (bl_magic)
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{
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case BL_MAGIC_CRBOOT_SLD:;
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// Set pwm to 0%, switch to gpio mode and restore pwm duty.
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u32 brightness = display_get_backlight_brightness();
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display_backlight_brightness(0, 1000);
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gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_GPIO);
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display_backlight_brightness(brightness, 0);
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break;
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default:
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display_end();
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}
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// Enable clock to USBD and init SDMMC1 to avoid hangs with bad hw inits.
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if (magic == 0xBAADF00D)
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if (bl_magic == BL_MAGIC_BROKEN_HWI)
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{
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_USBD);
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sdmmc_init(&sd_sdmmc, SDMMC_1, SDMMC_POWER_3_3, SDMMC_BUS_WIDTH_1, SDHCI_TIMING_SD_ID, 0);
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@ -20,6 +20,9 @@
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#include <utils/types.h>
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#define BL_MAGIC_CRBOOT_SLD 0x30444C53 // SLD0, seamless display type 0.
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#define BL_MAGIC_BROKEN_HWI 0xBAADF00D // Broken hwinit.
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void hw_init();
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void hw_reinit_workaround(bool coreboot, u32 magic);
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u32 hw_get_chip_id();
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@ -143,6 +143,7 @@ void check_power_off_from_hos()
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#define EXT_PAYLOAD_ADDR 0xC0000000
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#define RCM_PAYLOAD_ADDR (EXT_PAYLOAD_ADDR + ALIGN(PATCHED_RELOC_SZ, 0x10))
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#define COREBOOT_END_ADDR 0xD0000000
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#define COREBOOT_VER_OFF 0x41
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#define CBFS_DRAM_EN_ADDR 0x4003e000
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#define CBFS_DRAM_MAGIC 0x4452414D // "DRAM"
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@ -268,7 +269,12 @@ int launch_payload(char *path, bool update)
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else
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{
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reloc_patcher(PATCHED_RELOC_ENTRY, EXT_PAYLOAD_ADDR, 0x7000);
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hw_reinit_workaround(true, 0);
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// Get coreboot seamless display magic.
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u32 magic = 0;
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char *magic_ptr = buf + COREBOOT_VER_OFF;
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memcpy(&magic, magic_ptr + strlen(magic_ptr) - 4, 4);
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hw_reinit_workaround(true, magic);
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}
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// Some cards (Sandisk U1), do not like a fast power cycle. Wait min 100ms.
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