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clock: Add more defines and simplify some logic
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15afdf53e4
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@ -62,24 +62,31 @@ void ccplex_boot_cpu0(u32 entry)
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else
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_ccplex_enable_power_t210b01();
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if (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x40000000)) // PLLX_ENABLE.
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// Enable PLLX and set it to 300 MHz.
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if (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & PLLX_BASE_ENABLE)) // PLLX_ENABLE.
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{
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CLOCK(CLK_RST_CONTROLLER_PLLX_MISC_3) &= 0xFFFFFFF7; // Disable IDDQ.
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usleep(2);
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CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x80404E02;
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CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x404E02;
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// Bypass dividers.
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CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = PLLX_BASE_BYPASS | (4 << 20) | (78 << 8) | 2; // P div: 4 (5), N div: 78, M div: 2.
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// Disable bypass
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CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = (4 << 20) | (78 << 8) | 2;
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// Set PLLX_LOCK_ENABLE.
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CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) = (CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) & 0xFFFBFFFF) | 0x40000;
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CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x40404E02;
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// Enable PLLX.
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CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = PLLX_BASE_ENABLE | (4 << 20) | (78 << 8) | 2;
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}
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while (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x8000000))
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// Wait for PLL to stabilize.
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while (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & PLLX_BASE_LOCK))
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;
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// Configure MSELECT source and enable clock.
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// Configure MSELECT source and enable clock to 102MHz.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) & 0x1FFFFF00) | 6;
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) & ~BIT(CLK_V_MSELECT)) | BIT(CLK_V_MSELECT);
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = BIT(CLK_V_MSELECT);
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// Configure initial CPU clock frequency and enable clock.
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CLOCK(CLK_RST_CONTROLLER_CCLK_BURST_POLICY) = 0x20008888;
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CLOCK(CLK_RST_CONTROLLER_CCLK_BURST_POLICY) = 0x20008888; // PLLX_OUT0_LJ.
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CLOCK(CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER) = 0x80000000;
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = BIT(CLK_V_CPUG);
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@ -113,7 +120,7 @@ void ccplex_boot_cpu0(u32 entry)
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// MC(MC_TZ_SECURITY_CTRL) = 1;
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// Clear MSELECT reset.
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CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_V) &= ~BIT(CLK_V_MSELECT);
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_V_CLR) = BIT(CLK_V_MSELECT);
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// Clear NONCPU reset.
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CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = 0x20000000;
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// Clear CPU0 reset.
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@ -235,13 +235,13 @@ void clock_disable_sor1()
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void clock_enable_kfuse()
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{
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u32 kfuse_clk_unmask = ~BIT(CLK_H_KFUSE);
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CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) = (CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) & kfuse_clk_unmask) | BIT(CLK_H_KFUSE);
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) &= kfuse_clk_unmask;
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) & kfuse_clk_unmask) | BIT(CLK_H_KFUSE);
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usleep(10);
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CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) &= kfuse_clk_unmask;
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usleep(20);
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = BIT(CLK_H_KFUSE);
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_CLR) = BIT(CLK_H_KFUSE);
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_KFUSE);
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usleep(10); // Wait 10s to prevent glitching.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_KFUSE);
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usleep(20); // Wait 20s fo kfuse hw to init.
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}
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void clock_disable_kfuse()
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@ -163,9 +163,15 @@
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#define CLK_NOT_USED 0x0
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/*! PLL control and status bits */
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#define PLLX_BASE_LOCK BIT(27)
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#define PLLX_BASE_REF_DIS BIT(29)
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#define PLLX_BASE_ENABLE BIT(30)
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#define PLLX_BASE_BYPASS BIT(31)
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#define PLLCX_BASE_LOCK BIT(27)
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#define PLLCX_BASE_REF_DIS BIT(29)
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#define PLLCX_BASE_ENABLE BIT(30)
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#define PLLCX_BASE_BYPASS BIT(31)
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#define PLLA_OUT0_RSTN_CLR BIT(0)
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#define PLLA_OUT0_CLKEN BIT(1)
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