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bdk: clock: add apb/ahb clock control
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3dd12321f8
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10b479dc1c
@ -100,6 +100,14 @@ static clock_t _clock_sdmmc_legacy_tm = {
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CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM, CLK_Y_SDMMC_LEGACY_TM, 4, 66
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};
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static clock_t _clock_apbdma = {
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CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, CLK_H_APBDMA, 0, 0
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};
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static clock_t _clock_ahbdma = {
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CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, CLK_H_AHBDMA, 0, 0
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};
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static clock_t _clock_actmon = {
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CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON, CLK_V_ACTMON, 6, 0 // 19.2MHz.
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};
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@ -283,6 +291,26 @@ void clock_disable_pwm()
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clock_disable(&_clock_pwm);
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}
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void clock_enable_apbdma()
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{
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clock_enable(&_clock_apbdma);
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}
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void clock_disable_apbdma()
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{
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clock_disable(&_clock_apbdma);
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}
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void clock_enable_ahbdma()
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{
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clock_enable(&_clock_ahbdma);
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}
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void clock_disable_ahbdma()
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{
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clock_disable(&_clock_ahbdma);
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}
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void clock_enable_actmon()
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{
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clock_enable(&_clock_actmon);
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@ -660,6 +660,10 @@ void clock_enable_coresight();
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void clock_disable_coresight();
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void clock_enable_pwm();
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void clock_disable_pwm();
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void clock_enable_apbdma();
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void clock_disable_apbdma();
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void clock_enable_ahbdma();
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void clock_disable_ahbdma();
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void clock_enable_actmon();
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void clock_disable_actmon();
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