2018-11-30 21:20:15 +00:00
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/*
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* Copyright (c) 2018 naehrwert
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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2020-06-14 13:45:45 +00:00
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#include <utils/types.h>
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2018-11-30 21:20:15 +00:00
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#define SMMU_HEAP_ADDR 0xA0000000
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#define MC_INTSTATUS 0x0
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#define MC_INTMASK 0x4
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#define MC_ERR_STATUS 0x8
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#define MC_ERR_ADR 0xc
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#define MC_SMMU_CONFIG 0x10
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#define MC_SMMU_TLB_CONFIG 0x14
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#define MC_SMMU_PTC_CONFIG 0x18
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#define MC_SMMU_PTB_ASID 0x1c
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#define MC_SMMU_PTB_DATA 0x20
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#define MC_SMMU_TLB_FLUSH 0x30
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#define MC_SMMU_PTC_FLUSH 0x34
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#define MC_SMMU_ASID_SECURITY 0x38
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#define MC_SMMU_TSEC_ASID 0x294
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#define MC_SMMU_TRANSLATION_ENABLE_0 0x228
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#define MC_SMMU_TRANSLATION_ENABLE_1 0x22c
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#define MC_SMMU_TRANSLATION_ENABLE_2 0x230
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#define MC_SMMU_TRANSLATION_ENABLE_3 0x234
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#define MC_SMMU_TRANSLATION_ENABLE_4 0xb98
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#define SMMU_PDE_NEXT_SHIFT 28
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#define MC_SMMU_PTB_DATA_0_ASID_NONSECURE_SHIFT 29
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#define MC_SMMU_PTB_DATA_0_ASID_WRITABLE_SHIFT 30
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#define MC_SMMU_PTB_DATA_0_ASID_READABLE_SHIFT 31
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#define SMMU_PAGE_SHIFT 12
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#define SMMU_PAGE_SIZE (1 << SMMU_PAGE_SHIFT)
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#define SMMU_PDIR_COUNT 1024
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#define SMMU_PDIR_SIZE (sizeof(u32) * SMMU_PDIR_COUNT)
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#define SMMU_PTBL_COUNT 1024
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#define SMMU_PTBL_SIZE (sizeof(u32) * SMMU_PTBL_COUNT)
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#define SMMU_PDIR_SHIFT 12
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#define SMMU_PDE_SHIFT 12
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#define SMMU_PTE_SHIFT 12
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#define SMMU_PFN_MASK 0x000FFFFF
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#define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12)
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#define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22)
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#define SMMU_PDN_TO_ADDR(addr) ((pdn) << 22)
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#define _READABLE (1 << MC_SMMU_PTB_DATA_0_ASID_READABLE_SHIFT)
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#define _WRITABLE (1 << MC_SMMU_PTB_DATA_0_ASID_WRITABLE_SHIFT)
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#define _NONSECURE (1 << MC_SMMU_PTB_DATA_0_ASID_NONSECURE_SHIFT)
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#define _PDE_NEXT (1 << SMMU_PDE_NEXT_SHIFT)
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#define _MASK_ATTR (_READABLE | _WRITABLE | _NONSECURE)
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#define _PDIR_ATTR (_READABLE | _WRITABLE | _NONSECURE)
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#define _PDE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
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#define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR)
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#define _PTE_ATTR (_READABLE | _WRITABLE | _NONSECURE)
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#define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR)
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#define SMMU_MK_PDIR(page, attr) (((page) >> SMMU_PDIR_SHIFT) | (attr))
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#define SMMU_MK_PDE(page, attr) (((page) >> SMMU_PDE_SHIFT) | (attr))
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void *page_alloc(u32 num);
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u32 *smmu_alloc_pdir();
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void smmu_flush_regs();
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void smmu_flush_all();
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void smmu_init(u32 secmon_base);
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void smmu_enable();
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bool smmu_is_used();
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void smmu_exit();
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u32 *smmu_init_domain4(u32 dev_base, u32 asid);
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u32 *smmu_get_pte(u32 *pdir, u32 iova);
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void smmu_map(u32 *pdir, u32 addr, u32 page, int cnt, u32 attr);
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u32 *smmu_init_for_tsec();
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void smmu_deinit_for_tsec();
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