mirror/hekate
1
0
Fork 0
mirror of https://github.com/CTCaer/hekate.git synced 2024-11-02 11:30:41 +00:00
Code Issues Projects Releases Wiki Activity
e3eee73318
hekate/bdk/storage/sd.h

66 lines
1.6 KiB
C
Raw Normal View History

So it has come to this.
2018-05-01 05:15:48 +00:00
/*
bdk: add global header
2022-01-15 21:58:27 +00:00
* Copyright (c) 2018 naehrwert
bdk: sdmmc: add UHS DDR200 support The bdk flag BDK_SDMMC_UHS_DDR200_SUPPORT can be used to enable it. SD Card DDR200 (DDR208) support Proper procedure: 1. Check that Vendor Specific Command System is supported. Used as Enable DDR200 Bus. 2. Enable DDR200 bus mode via setting 14 to Group 2 via CMD6. Access Mode group is left to default 0 (SDR12). 3. Setup clock to 200 or 208 MHz. 4. Set host to DDR bus mode that supports such high clocks. Some hosts have special mode, others use DDR50 and others HS400. 5. Execute Tuning. The true validation that this value in Group 2 activates it, is that DDR50 bus and clocks/timings work fully after that point. On Tegra X1, that can be done with DDR50 host mode. Tuning though can't be done automatically on any DDR mode. So it needs to be done manually and selected tap will be applied from the biggest sampling window. Finally, all that simply works, because the marketing materials for DDR200 are basically overstatements to sell the feature. DDR200 is simply SDR104 in DDR mode, so sampling on rising and falling edge and with variable output data window. It can be supported by any host that is fast enough to support DDR at 200/208MHz and can do hw/sw tuning for finding the proper sampling window in that mode. Using a SDMMC controller on DDR200 mode at 400MHz, has latency allowance implications. The MC/EMC must be clocked enough to be able to serve the requests in time (512B in 1.28 ns).
2023-03-31 05:54:13 +00:00
* Copyright (c) 2018-2023 CTCaer
Whitespaces, fixes
2018-08-05 11:40:32 +00:00
*
bdk: add global header
2022-01-15 21:58:27 +00:00
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
sdmmc: Refactor again - Refactor various variables and defines - Removed Card/BGA and OEM ID info as they are static and useless - Commented out bkops functions completely as not used - Remove extra buf usage when there's already storage for storing that data - Optimize various functions to save space - Clean up useless or duplicate code
2021-02-06 01:41:35 +00:00
*
bdk: add global header
2022-01-15 21:58:27 +00:00
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
sdmmc: Refactor again - Refactor various variables and defines - Removed Card/BGA and OEM ID info as they are static and useless - Commented out bkops functions completely as not used - Remove extra buf usage when there's already storage for storing that data - Optimize various functions to save space - Clean up useless or duplicate code
2021-02-06 01:41:35 +00:00
*
bdk: add global header
2022-01-15 21:58:27 +00:00
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SD_H
#define SD_H
#include <storage/sdmmc.h>
#include <storage/sdmmc_driver.h>
#include <libs/fatfs/ff.h>
bdk: sdmmc: utilize block size defines
2024-03-12 13:47:14 +00:00
#define SD_BLOCKSIZE SDMMC_DAT_BLOCKSIZE
bdk: sdmmc: add missing sd block size define
2022-05-16 10:34:36 +00:00
bdk: add global header
2022-01-15 21:58:27 +00:00
enum
{
SD_INIT_FAIL = 0,
SD_1BIT_HS25 = 1,
SD_4BIT_HS25 = 2,
SD_UHS_SDR82 = 3,
bdk: sdmmc: add UHS DDR200 support The bdk flag BDK_SDMMC_UHS_DDR200_SUPPORT can be used to enable it. SD Card DDR200 (DDR208) support Proper procedure: 1. Check that Vendor Specific Command System is supported. Used as Enable DDR200 Bus. 2. Enable DDR200 bus mode via setting 14 to Group 2 via CMD6. Access Mode group is left to default 0 (SDR12). 3. Setup clock to 200 or 208 MHz. 4. Set host to DDR bus mode that supports such high clocks. Some hosts have special mode, others use DDR50 and others HS400. 5. Execute Tuning. The true validation that this value in Group 2 activates it, is that DDR50 bus and clocks/timings work fully after that point. On Tegra X1, that can be done with DDR50 host mode. Tuning though can't be done automatically on any DDR mode. So it needs to be done manually and selected tap will be applied from the biggest sampling window. Finally, all that simply works, because the marketing materials for DDR200 are basically overstatements to sell the feature. DDR200 is simply SDR104 in DDR mode, so sampling on rising and falling edge and with variable output data window. It can be supported by any host that is fast enough to support DDR at 200/208MHz and can do hw/sw tuning for finding the proper sampling window in that mode. Using a SDMMC controller on DDR200 mode at 400MHz, has latency allowance implications. The MC/EMC must be clocked enough to be able to serve the requests in time (512B in 1.28 ns).
2023-03-31 05:54:13 +00:00
SD_UHS_SDR104 = 4,
#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT
SD_UHS_DDR208 = 5
#endif
bdk: add global header
2022-01-15 21:58:27 +00:00
};
enum
{
SD_ERROR_INIT_FAIL = 0,
SD_ERROR_RW_FAIL = 1,
SD_ERROR_RW_RETRY = 2
};
extern sdmmc_t sd_sdmmc;
extern sdmmc_storage_t sd_storage;
extern FATFS sd_fs;
void sd_error_count_increment(u8 type);
u16 *sd_get_error_count();
bool sd_get_card_removed();
bool sd_get_card_initialized();
bool sd_get_card_mounted();
u32 sd_get_mode();
int sd_init_retry(bool power_cycle);
bool sd_initialize(bool power_cycle);
bool sd_mount();
void sd_unmount();
void sd_end();
bool sd_is_gpt();
void *sd_file_read(const char *path, u32 *fsize);
bdk: constify various args
2024-10-04 18:45:57 +00:00
int sd_save_to_file(const void *buf, u32 size, const char *filename);
bdk: add global header
2022-01-15 21:58:27 +00:00
#endif
Reference in New Issue Copy Permalink