hekate/bdk/soc/pmc.h

/*
 * Copyright (c) 2018 naehrwert
 * Copyright (c) 2018 st4rk
 * Copyright (c) 2018-2022 CTCaer
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef _PMC_H_
#define _PMC_H_

#include <utils/types.h>

/*! PMC registers. */
#define APBDEV_PMC_CNTRL 0x0
#define  PMC_CNTRL_MAIN_RST BIT(4)
#define APBDEV_PMC_SEC_DISABLE 0x4
#define APBDEV_PMC_PWRGATE_TOGGLE 0x30
#define APBDEV_PMC_PWRGATE_STATUS 0x38
#define APBDEV_PMC_NO_IOPOWER 0x44
#define  PMC_NO_IOPOWER_SDMMC1_IO_EN BIT(12)
#define  PMC_NO_IOPOWER_AUDIO_HV     BIT(18)
#define  PMC_NO_IOPOWER_GPIO_IO_EN   BIT(21)
#define APBDEV_PMC_SCRATCH0 0x50
#define  PMC_SCRATCH0_MODE_WARMBOOT BIT(0)
#define  PMC_SCRATCH0_MODE_RCM      BIT(1)
#define  PMC_SCRATCH0_MODE_PAYLOAD  BIT(29)
#define  PMC_SCRATCH0_MODE_FASTBOOT BIT(30)
#define  PMC_SCRATCH0_MODE_RECOVERY BIT(31)
#define  PMC_SCRATCH0_MODE_CUSTOM_ALL (PMC_SCRATCH0_MODE_RECOVERY | PMC_SCRATCH0_MODE_FASTBOOT | PMC_SCRATCH0_MODE_PAYLOAD)
#define APBDEV_PMC_SCRATCH1 0x54
#define APBDEV_PMC_SCRATCH20 0xA0
#define APBDEV_PMC_SECURE_SCRATCH4 0xC0
#define APBDEV_PMC_SECURE_SCRATCH5 0xC4
#define APBDEV_PMC_PWR_DET_VAL 0xE4
#define  PMC_PWR_DET_SDMMC1_IO_EN BIT(12)
#define  PMC_PWR_DET_AUDIO_HV     BIT(18)
#define  PMC_PWR_DET_GPIO_IO_EN   BIT(21)
#define APBDEV_PMC_DDR_PWR 0xE8
#define APBDEV_PMC_USB_AO 0xF0
#define APBDEV_PMC_CRYPTO_OP 0xF4
#define  PMC_CRYPTO_OP_SE_ENABLE  0
#define  PMC_CRYPTO_OP_SE_DISABLE 1
#define APBDEV_PMC_SCRATCH33 0x120
#define APBDEV_PMC_SCRATCH37 0x130
#define  PMC_SCRATCH37_KERNEL_PANIC_MAGIC 0x4E415054
#define APBDEV_PMC_SCRATCH40 0x13C
#define APBDEV_PMC_OSC_EDPD_OVER 0x1A4
#define  PMC_OSC_EDPD_OVER_OSC_CTRL_OVER 0x400000
#define APBDEV_PMC_CLK_OUT_CNTRL 0x1A8
#define  PMC_CLK_OUT_CNTRL_CLK1_FORCE_EN BIT(2)
#define APBDEV_PMC_RST_STATUS 0x1B4
#define  PMC_RST_STATUS_MASK 0x7
#define  PMC_RST_STATUS_POR 0
#define  PMC_RST_STATUS_WATCHDOG 1
#define  PMC_RST_STATUS_SENSOR 2
#define  PMC_RST_STATUS_SW_MAIN 3
#define  PMC_RST_STATUS_LP0 4
#define  PMC_RST_STATUS_AOTAG 5
#define APBDEV_PMC_IO_DPD_REQ 0x1B8
#define  PMC_IO_DPD_REQ_DPD_OFF BIT(30)
#define APBDEV_PMC_IO_DPD2_REQ 0x1C0
#define APBDEV_PMC_VDDP_SEL 0x1CC
#define APBDEV_PMC_DDR_CFG 0x1D0
#define APBDEV_PMC_SECURE_SCRATCH6 0x224
#define APBDEV_PMC_SECURE_SCRATCH7 0x228
#define APBDEV_PMC_SCRATCH45 0x234
#define APBDEV_PMC_SCRATCH46 0x238
#define APBDEV_PMC_SCRATCH49 0x244
#define APBDEV_PMC_TSC_MULT 0x2B4
#define APBDEV_PMC_SEC_DISABLE2 0x2C4
#define APBDEV_PMC_WEAK_BIAS 0x2C8
#define APBDEV_PMC_REG_SHORT 0x2CC
#define APBDEV_PMC_SEC_DISABLE3 0x2D8
#define APBDEV_PMC_SECURE_SCRATCH21 0x334
#define  PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT 0x10
#define APBDEV_PMC_SECURE_SCRATCH32 0x360
#define APBDEV_PMC_SECURE_SCRATCH49 0x3A4
#define APBDEV_PMC_CNTRL2 0x440
#define  PMC_CNTRL2_HOLD_CKE_LOW_EN 0x1000
#define APBDEV_PMC_IO_DPD3_REQ 0x45C
#define APBDEV_PMC_IO_DPD4_REQ 0x464
#define APBDEV_PMC_UTMIP_PAD_CFG1 0x4C4
#define APBDEV_PMC_UTMIP_PAD_CFG3 0x4CC
#define APBDEV_PMC_DDR_CNTRL 0x4E4
#define APBDEV_PMC_SEC_DISABLE4 0x5B0
#define APBDEV_PMC_SEC_DISABLE5 0x5B4
#define APBDEV_PMC_SEC_DISABLE6 0x5B8
#define APBDEV_PMC_SEC_DISABLE7 0x5BC
#define APBDEV_PMC_SEC_DISABLE8 0x5C0
#define APBDEV_PMC_SEC_DISABLE9 0x5C4
#define APBDEV_PMC_SEC_DISABLE10 0x5C8
#define APBDEV_PMC_SCRATCH188 0x810
#define APBDEV_PMC_SCRATCH190 0x818
#define APBDEV_PMC_SCRATCH200 0x840
#define APBDEV_PMC_SECURE_SCRATCH108 0xB08
#define APBDEV_PMC_SECURE_SCRATCH109 0xB0C
#define APBDEV_PMC_SECURE_SCRATCH110 0xB10
#define APBDEV_PMC_TZRAM_PWR_CNTRL 0xBE8
#define  PMC_TZRAM_PWR_CNTRL_SD BIT(0)
#define APBDEV_PMC_TZRAM_SEC_DISABLE 0xBEC
#define APBDEV_PMC_TZRAM_NON_SEC_DISABLE 0xBF0
#define  PMC_TZRAM_DISABLE_REG_WRITE BIT(0)
#define  PMC_TZRAM_DISABLE_REG_READ  BIT(1)

typedef enum _pmc_sec_lock_t
{
	PMC_SEC_LOCK_MISC       = BIT(0),
	PMC_SEC_LOCK_LP0_PARAMS = BIT(1),
	PMC_SEC_LOCK_RST_VECTOR = BIT(2),
	PMC_SEC_LOCK_CARVEOUTS  = BIT(3),
	PMC_SEC_LOCK_TZ_CMAC_W  = BIT(4),
	PMC_SEC_LOCK_TZ_CMAC_R  = BIT(5),
	PMC_SEC_LOCK_TZ_KEK_W   = BIT(6),
	PMC_SEC_LOCK_TZ_KEK_R   = BIT(7),
	PMC_SEC_LOCK_SE_SRK     = BIT(8),
} pmc_sec_lock_t;

typedef enum _pmc_power_rail_t
{
	POWER_RAIL_CRAIL = 0,
	POWER_RAIL_3D0   = 1,
	POWER_RAIL_VENC  = 2,
	POWER_RAIL_PCIE  = 3,
	POWER_RAIL_VDEC  = 4,
	POWER_RAIL_L2C   = 5,
	POWER_RAIL_MPE   = 6,
	POWER_RAIL_HEG   = 7,
	POWER_RAIL_SATA  = 8,
	POWER_RAIL_CE1   = 9,
	POWER_RAIL_CE2   = 10,
	POWER_RAIL_CE3   = 11,
	POWER_RAIL_CELP  = 12,
	POWER_RAIL_3D1   = 13,
	POWER_RAIL_CE0   = 14,
	POWER_RAIL_C0NC  = 15,
	POWER_RAIL_C1NC  = 16,
	POWER_RAIL_SOR   = 17,
	POWER_RAIL_DIS   = 18,
	POWER_RAIL_DISB  = 19,
	POWER_RAIL_XUSBA = 20,
	POWER_RAIL_XUSBB = 21,
	POWER_RAIL_XUSBC = 22,
	POWER_RAIL_VIC   = 23,
	POWER_RAIL_IRAM  = 24,
	POWER_RAIL_NVDEC = 25,
	POWER_RAIL_NVJPG = 26,
	POWER_RAIL_AUD   = 27,
	POWER_RAIL_DFD   = 28,
	POWER_RAIL_VE2   = 29
} pmc_power_rail_t;

void pmc_scratch_lock(pmc_sec_lock_t lock_mask);
int  pmc_enable_partition(pmc_power_rail_t part, u32 enable);

#endif