Jit_LoadStoreFloating: lfXXX

This commit is contained in:
MerryMage 2018-10-15 21:01:47 +01:00
parent 36790ad3ad
commit f564da7233
3 changed files with 22 additions and 31 deletions

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@ -756,7 +756,6 @@ u8* Jit64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
js.downcountAmount += opinfo->numCycles; js.downcountAmount += opinfo->numCycles;
js.fastmemLoadStore = nullptr; js.fastmemLoadStore = nullptr;
js.fixupExceptionHandler = false; js.fixupExceptionHandler = false;
js.revertFprLoad = -1;
if (!SConfig::GetInstance().bEnableDebugging) if (!SConfig::GetInstance().bEnableDebugging)
js.downcountAmount += PatchEngine::GetSpeedhackCycles(js.compilerPC); js.downcountAmount += PatchEngine::GetSpeedhackCycles(js.compilerPC);
@ -921,13 +920,9 @@ u8* Jit64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
gpr.Revert(); gpr.Revert();
fpr.Revert(); fpr.Revert();
gpr.Flush();
fpr.Flush();
BitSet32 gprToFlush = BitSet32::AllTrue(32);
BitSet32 fprToFlush = BitSet32::AllTrue(32);
if (js.revertFprLoad >= 0)
fprToFlush[js.revertFprLoad] = false;
gpr.Flush(RegCache::FlushMode::MaintainState, gprToFlush);
fpr.Flush(RegCache::FlushMode::MaintainState, fprToFlush);
MOV(32, PPCSTATE(pc), Imm32(op.address)); MOV(32, PPCSTATE(pc), Imm32(op.address));
WriteExceptionExit(); WriteExceptionExit();
SwitchToNearCode(); SwitchToNearCode();

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@ -30,25 +30,27 @@ void Jit64::lfXXX(UGeckoInstruction inst)
FALLBACK_IF(!indexed && !a); FALLBACK_IF(!indexed && !a);
gpr.BindToRegister(a, true, update);
s32 offset = 0; s32 offset = 0;
OpArg addr = gpr.R(a); RCOpArg addr = gpr.Bind(a, update ? RCMode::ReadWrite : RCMode::Read);
RegCache::Realize(addr);
if (update && jo.memcheck) if (update && jo.memcheck)
{ {
addr = R(RSCRATCH2); MOV(32, R(RSCRATCH2), addr);
MOV(32, addr, gpr.R(a)); addr = RCOpArg::R(RSCRATCH2);
} }
if (indexed) if (indexed)
{ {
RCOpArg Rb = gpr.Use(b, RCMode::Read);
RegCache::Realize(Rb);
if (update) if (update)
{ {
ADD(32, addr, gpr.R(b)); ADD(32, addr, Rb);
} }
else else
{ {
addr = R(RSCRATCH2); MOV_sum(32, RSCRATCH2, a ? addr.Location() : Imm32(0), Rb);
MOV_sum(32, RSCRATCH2, a ? gpr.R(a) : Imm32(0), gpr.R(b)); addr = RCOpArg::R(RSCRATCH2);
} }
} }
else else
@ -59,13 +61,9 @@ void Jit64::lfXXX(UGeckoInstruction inst)
offset = (s16)inst.SIMM_16; offset = (s16)inst.SIMM_16;
} }
fpr.Lock(d); RCMode Rd_mode = !single ? RCMode::ReadWrite : RCMode::Write;
if (jo.memcheck && single) RCX64Reg Rd = jo.memcheck && single ? fpr.RevertableBind(d, Rd_mode) : fpr.Bind(d, Rd_mode);
{ RegCache::Realize(Rd);
fpr.StoreFromRegister(d);
js.revertFprLoad = d;
}
fpr.BindToRegister(d, !single);
BitSet32 registersInUse = CallerSavedRegistersInUse(); BitSet32 registersInUse = CallerSavedRegistersInUse();
if (update && jo.memcheck) if (update && jo.memcheck)
registersInUse[RSCRATCH2] = true; registersInUse[RSCRATCH2] = true;
@ -73,17 +71,19 @@ void Jit64::lfXXX(UGeckoInstruction inst)
if (single) if (single)
{ {
ConvertSingleToDouble(fpr.RX(d), RSCRATCH, true); ConvertSingleToDouble(Rd, RSCRATCH, true);
} }
else else
{ {
MOVQ_xmm(XMM0, R(RSCRATCH)); MOVQ_xmm(XMM0, R(RSCRATCH));
MOVSD(fpr.RX(d), R(XMM0)); MOVSD(Rd, R(XMM0));
} }
if (update && jo.memcheck) if (update && jo.memcheck)
MOV(32, gpr.R(a), addr); {
fpr.UnlockAll(); RCX64Reg Ra = gpr.Bind(a, RCMode::Write);
gpr.UnlockAll(); RegCache::Realize(Ra);
MOV(32, Ra, addr);
}
} }
void Jit64::stfXXX(UGeckoInstruction inst) void Jit64::stfXXX(UGeckoInstruction inst)

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@ -70,10 +70,6 @@ protected:
// so just fixup that branch instead of testing for a DSI again. // so just fixup that branch instead of testing for a DSI again.
bool fixupExceptionHandler; bool fixupExceptionHandler;
Gen::FixupBranch exceptionHandler; Gen::FixupBranch exceptionHandler;
// If these are set, we've stored the old value of a register which will be loaded in
// revertLoad,
// which lets us revert it on the exception path.
int revertFprLoad;
bool assumeNoPairedQuantize; bool assumeNoPairedQuantize;
std::map<u8, u32> constantGqr; std::map<u8, u32> constantGqr;