From cf5fc063ce28cfddeaf539eb175a6a2fe1179c57 Mon Sep 17 00:00:00 2001 From: magumagu9 Date: Tue, 10 Feb 2009 12:20:30 +0000 Subject: [PATCH] JitIL: Make LoadCarry work correctly. git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@2202 8ced0084-cf51-0410-be5f-012b33b47a6e --- Source/Core/Core/Src/PowerPC/Jit64IL/IR.cpp | 11 ++++++++++- Source/Core/Core/Src/PowerPC/Jit64IL/Jit_Integer.cpp | 2 -- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/Source/Core/Core/Src/PowerPC/Jit64IL/IR.cpp b/Source/Core/Core/Src/PowerPC/Jit64IL/IR.cpp index 1e6aa1f892..16c3223f06 100644 --- a/Source/Core/Core/Src/PowerPC/Jit64IL/IR.cpp +++ b/Source/Core/Core/Src/PowerPC/Jit64IL/IR.cpp @@ -259,7 +259,7 @@ InstLoc IRBuilder::FoldZeroOp(unsigned Opcode, unsigned extra) { } if (Opcode == LoadCarry) { if (!CarryCache) - CarryCache = EmitZeroOp(LoadGReg, extra); + CarryCache = EmitZeroOp(LoadCarry, extra); return CarryCache; } if (Opcode == LoadCR) { @@ -1408,6 +1408,15 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) { Jit->MOV(32, R(reg), M(&MSR)); RI.regs[reg] = I; break; + } + case LoadCarry: { + if (!thisUsed) break; + X64Reg reg = regFindFreeReg(RI); + Jit->MOV(32, R(reg), M(&PowerPC::ppcState.spr[SPR_XER])); + Jit->SHR(32, R(reg), Imm8(29)); + Jit->AND(32, R(reg), Imm8(1)); + RI.regs[reg] = I; + break; } case StoreGReg: { unsigned ppcreg = *I >> 16; diff --git a/Source/Core/Core/Src/PowerPC/Jit64IL/Jit_Integer.cpp b/Source/Core/Core/Src/PowerPC/Jit64IL/Jit_Integer.cpp index c22768e9e7..c49187eff0 100644 --- a/Source/Core/Core/Src/PowerPC/Jit64IL/Jit_Integer.cpp +++ b/Source/Core/Core/Src/PowerPC/Jit64IL/Jit_Integer.cpp @@ -341,8 +341,6 @@ void Jit64::addzex(UGeckoInstruction inst) { - Default(inst); return; - // FIXME: There's a bug in here somewhere! INSTRUCTION_START IREmitter::InstLoc lhs = ibuild.EmitLoadGReg(inst.RA), val, newcarry;