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JitArm64: CR field cleanup.

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This commit is contained in:
degasus 2016-10-27 21:48:52 +02:00
parent 3405f5ac1a
commit c69903eb42
4 changed files with 13 additions and 17 deletions
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3
Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp
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@ -313,8 +313,7 @@ void JitArm64::fcmpX(UGeckoInstruction inst)
} }
SetJumpTarget(continue1); SetJumpTarget(continue1);
STR(INDEX_UNSIGNED, XA, PPC_REG, STR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val[crf]));
PPCSTATE_OFF(cr_val[0]) + (sizeof(PowerPC::ppcState.cr_val[0]) * crf));
gpr.Unlock(WA); gpr.Unlock(WA);
} }

9
Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp
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@ -423,8 +423,7 @@ void JitArm64::cmp(UGeckoInstruction inst)
SXTW(XB, RB); SXTW(XB, RB);
SUB(XA, XA, XB); SUB(XA, XA, XB);
STR(INDEX_UNSIGNED, XA, PPC_REG, STR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val[crf]));
PPCSTATE_OFF(cr_val[0]) + (sizeof(PowerPC::ppcState.cr_val[0]) * crf));
gpr.Unlock(WA, WB); gpr.Unlock(WA, WB);
} }
@ -451,8 +450,7 @@ void JitArm64::cmpl(UGeckoInstruction inst)
ARM64Reg WA = gpr.GetReg(); ARM64Reg WA = gpr.GetReg();
ARM64Reg XA = EncodeRegTo64(WA); ARM64Reg XA = EncodeRegTo64(WA);
SUB(XA, EncodeRegTo64(gpr.R(a)), EncodeRegTo64(gpr.R(b))); SUB(XA, EncodeRegTo64(gpr.R(a)), EncodeRegTo64(gpr.R(b)));
STR(INDEX_UNSIGNED, XA, PPC_REG, STR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val[crf]));
PPCSTATE_OFF(cr_val[0]) + (sizeof(PowerPC::ppcState.cr_val[0]) * crf));
gpr.Unlock(WA); gpr.Unlock(WA);
} }
@ -502,8 +500,7 @@ void JitArm64::cmpli(UGeckoInstruction inst)
SUBI2R(XA, EncodeRegTo64(gpr.R(a)), inst.UIMM, XA); SUBI2R(XA, EncodeRegTo64(gpr.R(a)), inst.UIMM, XA);
STR(INDEX_UNSIGNED, XA, PPC_REG, STR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val[crf]));
PPCSTATE_OFF(cr_val[0]) + (sizeof(PowerPC::ppcState.cr_val[0]) * crf));
gpr.Unlock(WA); gpr.Unlock(WA);
} }

16
Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp
View File

@ -417,7 +417,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
ARM64Reg WA = gpr.GetReg(); ARM64Reg WA = gpr.GetReg();
ARM64Reg XA = EncodeRegTo64(WA); ARM64Reg XA = EncodeRegTo64(WA);
LDR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val) + 8 * field); LDR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val[field]));
switch (bit) switch (bit)
{ {
case CR_SO_BIT: case CR_SO_BIT:
@ -436,7 +436,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
AND(XA, XA, 64 - 63, 62, true); // XA & ~(1<<62) AND(XA, XA, 64 - 63, 62, true); // XA & ~(1<<62)
break; break;
} }
STR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val) + 8 * field); STR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val[field]));
gpr.Unlock(WA); gpr.Unlock(WA);
return; return;
} }
@ -450,7 +450,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
ARM64Reg WA = gpr.GetReg(); ARM64Reg WA = gpr.GetReg();
ARM64Reg XA = EncodeRegTo64(WA); ARM64Reg XA = EncodeRegTo64(WA);
LDR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val) + 8 * field); LDR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val[field]));
if (bit != CR_GT_BIT) if (bit != CR_GT_BIT)
{ {
@ -483,7 +483,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
ORR(XA, XA, 32, 0, true); // XA | 1<<32 ORR(XA, XA, 32, 0, true); // XA | 1<<32
STR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val) + 8 * field); STR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val[field]));
gpr.Unlock(WA); gpr.Unlock(WA);
return; return;
} }
@ -509,7 +509,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
ARM64Reg WC = gpr.GetReg(); ARM64Reg WC = gpr.GetReg();
ARM64Reg XC = EncodeRegTo64(WC); ARM64Reg XC = EncodeRegTo64(WC);
LDR(INDEX_UNSIGNED, XC, PPC_REG, PPCSTATE_OFF(cr_val) + 8 * field); LDR(INDEX_UNSIGNED, XC, PPC_REG, PPCSTATE_OFF(cr_val[field]));
switch (bit) switch (bit)
{ {
case CR_SO_BIT: // check bit 61 set case CR_SO_BIT: // check bit 61 set
@ -565,7 +565,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
int field = inst.CRBD >> 2; int field = inst.CRBD >> 2;
int bit = 3 - (inst.CRBD & 3); int bit = 3 - (inst.CRBD & 3);
LDR(INDEX_UNSIGNED, XB, PPC_REG, PPCSTATE_OFF(cr_val) + 8 * field); LDR(INDEX_UNSIGNED, XB, PPC_REG, PPCSTATE_OFF(cr_val[field]));
// Gross but necessary; if the input is totally zero and we set SO or LT, // Gross but necessary; if the input is totally zero and we set SO or LT,
// or even just add the (1<<32), GT will suddenly end up set without us // or even just add the (1<<32), GT will suddenly end up set without us
@ -603,7 +603,7 @@ void JitArm64::crXXX(UGeckoInstruction inst)
} }
ORR(XA, XA, 32, 0, true); // XA | 1<<32 ORR(XA, XA, 32, 0, true); // XA | 1<<32
STR(INDEX_UNSIGNED, XB, PPC_REG, PPCSTATE_OFF(cr_val) + 8 * field); STR(INDEX_UNSIGNED, XB, PPC_REG, PPCSTATE_OFF(cr_val[field]));
gpr.Unlock(WA); gpr.Unlock(WA);
gpr.Unlock(WB); gpr.Unlock(WB);
@ -653,7 +653,7 @@ void JitArm64::mtcrf(UGeckoInstruction inst)
} }
LDR(XA, XB, ArithOption(XA, true)); LDR(XA, XB, ArithOption(XA, true));
STR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val) + 8 * i); STR(INDEX_UNSIGNED, XA, PPC_REG, PPCSTATE_OFF(cr_val[i]));
} }
} }
gpr.Unlock(WA, WB); gpr.Unlock(WA, WB);

2
Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp
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@ -629,7 +629,7 @@ void JitArm64::GenMfcr()
const u8* start = GetCodePtr(); const u8* start = GetCodePtr();
for (int i = 0; i < 8; i++) for (int i = 0; i < 8; i++)
{ {
LDR(INDEX_UNSIGNED, X1, PPC_REG, PPCSTATE_OFF(cr_val) + 8 * i); LDR(INDEX_UNSIGNED, X1, PPC_REG, PPCSTATE_OFF(cr_val[i]));
// SO // SO
if (i == 0) if (i == 0)