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Merge pull request #10454 from Pokechu22/pi-fifo-reset

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ProcessorInterface: Implement PI_FIFO_RESET
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JMC47 2022-05-14 00:53:48 -04:00 committed by GitHub
commit be75273ad4
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2 changed files with 6 additions and 2 deletions
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6
Source/Core/Core/HW/ProcessorInterface.cpp
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@ -18,6 +18,7 @@
#include "Core/IOS/IOS.h" #include "Core/IOS/IOS.h"
#include "Core/IOS/STM/STM.h" #include "Core/IOS/STM/STM.h"
#include "Core/PowerPC/PowerPC.h" #include "Core/PowerPC/PowerPC.h"
#include "VideoCommon/Fifo.h"
namespace ProcessorInterface namespace ProcessorInterface
{ {
@ -111,7 +112,10 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
mmio->Register(base | PI_FIFO_RESET, MMIO::InvalidRead<u32>(), mmio->Register(base | PI_FIFO_RESET, MMIO::InvalidRead<u32>(),
MMIO::ComplexWrite<u32>([](u32, u32 val) { MMIO::ComplexWrite<u32>([](u32, u32 val) {
WARN_LOG_FMT(PROCESSORINTERFACE, "Fifo reset ({:08x})", val); // Used by GXAbortFrame
INFO_LOG_FMT(PROCESSORINTERFACE, "Wrote PI_FIFO_RESET: {:08x}", val);
if ((val & 1) != 0)
Fifo::ResetVideoBuffer();
})); }));
mmio->Register(base | PI_RESET_CODE, MMIO::ComplexRead<u32>([](u32) { mmio->Register(base | PI_RESET_CODE, MMIO::ComplexRead<u32>([](u32) {

2
Source/Core/Core/HW/ProcessorInterface.h
View File

@ -46,7 +46,7 @@ enum
PI_FIFO_BASE = 0x0C, PI_FIFO_BASE = 0x0C,
PI_FIFO_END = 0x10, PI_FIFO_END = 0x10,
PI_FIFO_WPTR = 0x14, PI_FIFO_WPTR = 0x14,
PI_FIFO_RESET = 0x18, // ??? - GXAbortFrame writes to it PI_FIFO_RESET = 0x18, // Used by GXAbortFrame
PI_RESET_CODE = 0x24, PI_RESET_CODE = 0x24,
PI_FLIPPER_REV = 0x2C, PI_FLIPPER_REV = 0x2C,
PI_FLIPPER_UNK = 0x30 // BS1 writes 0x0245248A to it - prolly some bootstrap thing PI_FLIPPER_UNK = 0x30 // BS1 writes 0x0245248A to it - prolly some bootstrap thing