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https://github.com/dolphin-emu/dolphin.git
synced 2025-01-26 12:35:27 +00:00
Got rid of loop step + added some comments
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@2928 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
nakeee
parent
65daec3554
commit
7dccebfef2
@ -138,6 +138,12 @@ void ret(const UDSPInstruction& opc)
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}
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}
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// RTI
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// 0000 0010 1111 1111
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// Return from exception. Pops stored status register $sr from data stack
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// $st1 and program counter PC from call stack $st0 and sets $pc to this
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// location.
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// FIXME: is it also conditional? unknown opcodes 0x02fx
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void rti(const UDSPInstruction& opc)
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{
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g_dsp.r[DSP_REG_SR] = dsp_reg_load_stack(DSP_STACK_D);
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@ -155,37 +161,64 @@ void halt(const UDSPInstruction& opc)
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g_dsp.pc = g_dsp.err_pc;
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}
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// LOOP handling: Loop stack is used to control execution of repeated blocks of
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// instructions. Whenever there is value on stack $st2 and current PC is equal
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// value at $st2, then value at stack $st3 is decremented. If value is not zero
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// then PC is modified with calue from call stack $st0. Otherwise values from
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// callstack $st0 and both loop stacks $st2 and $st3 are poped and execution
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// continues at next opcode.
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// LOOP $R
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// 0000 0000 010r rrrr
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// Repeatedly execute following opcode until counter specified by value
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// from register $R reaches zero. Each execution decrement counter. Register
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// $R remains unchanged. If register $R is set to zero at the beginning of loop
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// then looped instruction will not get executed.
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void loop(const UDSPInstruction& opc)
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{
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u16 reg = opc.hex & 0x1f;
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u16 cnt = g_dsp.r[reg];
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u16 loop_pc = g_dsp.pc;
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while (cnt--)
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if (cnt)
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{
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gdsp_loop_step();
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g_dsp.pc = loop_pc;
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dsp_reg_store_stack(0, g_dsp.pc);
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dsp_reg_store_stack(2, loop_pc);
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dsp_reg_store_stack(3, cnt);
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}
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// g_dsp.pc = loop_pc;
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g_dsp.pc += opSize[dsp_peek_code()];
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}
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// LOOPI #I
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// 0001 0000 iiii iiii
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// Repeatedly execute following opcode until counter specified by
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// immediate value I reaches zero. Each execution decrement counter. If
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// immediate value I is set to zero at the beginning of loop then looped
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// instruction will not get executed.
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void loopi(const UDSPInstruction& opc)
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{
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u16 cnt = opc.hex & 0xff;
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u16 loop_pc = g_dsp.pc;
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while (cnt--)
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if (cnt)
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{
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gdsp_loop_step();
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g_dsp.pc = loop_pc;
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dsp_reg_store_stack(0, g_dsp.pc);
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dsp_reg_store_stack(2, loop_pc);
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dsp_reg_store_stack(3, cnt);
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}
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// g_dsp.pc = loop_pc;
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g_dsp.pc += opSize[dsp_peek_code()];
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}
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// BLOOP $R, addrA
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// 0000 0000 011r rrrr
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// aaaa aaaa aaaa aaaa
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// Repeatedly execute block of code starting at following opcode until
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// counter specified by value from register $R reaches zero. Block ends at
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// specified address addrA inclusive, ie. opcode at addrA is the last opcode
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// included in loop. Counter is pushed on loop stack $st3, end of block address
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// is pushed on loop stack $st2 and repeat address is pushed on call stack $st0.
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// Up to 4 nested loops is allowed.
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void bloop(const UDSPInstruction& opc)
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{
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u16 reg = opc.hex & 0x1f;
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@ -205,6 +238,15 @@ void bloop(const UDSPInstruction& opc)
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}
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}
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// BLOOPI #I, addrA
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// 0001 0001 iiii iiii
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// aaaa aaaa aaaa aaaa
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// Repeatedly execute block of code starting at following opcode until
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// counter specified by immediate value I reaches zero. Block ends at specified
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// address addrA inclusive, ie. opcode at addrA is the last opcode included in
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// loop. Counter is pushed on loop stack $st3, end of block address is pushed
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// on loop stack $st2 and repeat address is pushed on call stack $st0. Up to 4
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// nested loops is allowed.
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void bloopi(const UDSPInstruction& opc)
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{
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u16 cnt = opc.hex & 0xff;
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@ -344,8 +386,7 @@ void srri(const UDSPInstruction& opc)
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// SRRN @$D, $S
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// 0001 1011 1dds ssss
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// Store value from source register $S to a memory location pointed by
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// addressing register $D. Add indexing register $(0x4+D) to register $D.
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// addressing register $D. Add DSP_REG_IX0 register to register $D.
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// FIXME: Perform additional operation depending on source register.
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void srrn(const UDSPInstruction& opc)
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{
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@ -354,7 +395,7 @@ void srrn(const UDSPInstruction& opc)
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u16 val = dsp_op_read_reg(sreg);
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dsp_dmem_write(g_dsp.r[dreg], val);
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g_dsp.r[dreg] += g_dsp.r[dreg + 4];
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g_dsp.r[dreg] += g_dsp.r[DSP_REG_IX0 + dreg];
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}
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// ILRR $acD.m, @$arS
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@ -426,11 +467,11 @@ void lri(const UDSPInstruction& opc)
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// LRIS $(0x18+D), #I
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// 0000 1ddd iiii iiii
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// Load immediate value I (8-bit sign extended) to accumulator register$(0x18+D).
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// Load immediate value I (8-bit sign extended) to accumulator register.
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// FIXME: Perform additional operation depending on destination register.
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void lris(const UDSPInstruction& opc)
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{
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u8 reg = ((opc.hex >> 8) & 0x7) + 0x18;
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u8 reg = ((opc.hex >> 8) & 0x7) + DSP_REG_AXL0;
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u16 imm = (s8)opc.hex;
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dsp_op_write_reg(reg, imm);
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}
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@ -516,7 +557,7 @@ void clrl(const UDSPInstruction& opc)
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g_dsp.r[reg] &= 0x0000;
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// Should this be 64bit?
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// nakee: it says the whole reg in doddie's doc sounds weird
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// nakee: it says the whole reg in duddie's doc sounds weird
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Update_SR_Register64((s64)reg);
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}
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@ -525,7 +566,7 @@ void clrl(const UDSPInstruction& opc)
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// Clears product register $prod.
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void clrp(const UDSPInstruction& opc)
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{
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// Magic numbers taken from doddie's doc
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// Magic numbers taken from duddie's doc
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g_dsp.r[0x14] = 0x0000;
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g_dsp.r[0x15] = 0xfff0;
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g_dsp.r[0x16] = 0x00ff;
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@ -687,6 +728,10 @@ void movax(const UDSPInstruction& opc)
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Update_SR_Register64(acx);
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}
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// XORR $acD.m, $axS.h
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// 0011 00sd xxxx xxxx
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// Logic XOR (exclusive or) middle part of accumulator $acD.m with
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// high part of secondary accumulator $axS.h.
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void xorr(const UDSPInstruction& opc)
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{
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u8 sreg = (opc.hex >> 9) & 0x1;
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@ -699,7 +744,7 @@ void xorr(const UDSPInstruction& opc)
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// ANDR $acD.m, $axS.h
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// 0011 01sd xxxx xxxx
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// Logic AND middle part of accumulator $acD.m with hight part of
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// Logic AND middle part of accumulator $acD.m with high part of
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// secondary accumulator $axS.h.
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void andr(const UDSPInstruction& opc)
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{
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@ -711,6 +756,11 @@ void andr(const UDSPInstruction& opc)
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tsta(dreg);
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}
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// ORR $acD.m, $axS.h
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// 0011 10sd xxxx xxxx
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// Logic OR middle part of accumulator $acD.m with high part of
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// secondary accumulator $axS.h.
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void orr(const UDSPInstruction& opc)
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{
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u8 sreg = (opc.hex >> 9) & 0x1;
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@ -1379,7 +1429,7 @@ void mul(const UDSPInstruction& opc)
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dsp_set_long_prod(prod);
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// FIXME: no update in doddie's docs
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// FIXME: no update in duddie's docs
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Update_SR_Register64(prod);
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}
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@ -1400,7 +1450,7 @@ void mulac(const UDSPInstruction& opc)
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s64 prod = dsp_get_ax_l(sreg) * dsp_get_ax_h(sreg) * GetMultiplyModifier();
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dsp_set_long_prod(prod);
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// FIXME: no update in doddie's docs
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// FIXME: no update in duddie's docs
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Update_SR_Register64(prod);
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}
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@ -1626,7 +1676,7 @@ void msubc(const UDSPInstruction& opc)
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// Store value from register $(0x18+S) to a memory pointed by address M.
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// (8-bit sign extended).
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// FIXME: Perform additional operation depending on destination register.
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// Note: pc+=2 in doddie's doc seems wrong
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// Note: pc+=2 in duddie's doc seems wrong
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void srs(const UDSPInstruction& opc)
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{
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u8 reg = ((opc.hex >> 8) & 0x7) + 0x18;
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@ -1639,7 +1689,7 @@ void srs(const UDSPInstruction& opc)
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// Move value from data memory pointed by address M (8-bit sign
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// extended) to register $(0x18+D).
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// FIXME: Perform additional operation depending on destination register.
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// Note: pc+=2 in doddie's doc seems wrong
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// Note: pc+=2 in duddie's doc seems wrong
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void lrs(const UDSPInstruction& opc)
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{
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u8 reg = ((opc.hex >> 8) & 0x7) + 0x18;
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@ -66,6 +66,10 @@ void nop(const UDSPInstruction& opc) {if(opc.hex) DSPInterpreter::unknown(opc);}
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DSPOPCTemplate opcodes[] =
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{
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{"NOP", 0x0000, 0xffff, nop, nop, 1, 0, {}, NULL, NULL},
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{"DAR", 0x0004, 0xfffc, DSPInterpreter::dar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL},
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{"IAR", 0x0008, 0xfffc, DSPInterpreter::iar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL},
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{"HALT", 0x0021, 0xffff, DSPInterpreter::halt, nop, 1, 0, {}, NULL, NULL},
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{"RETNS", 0x02d0, 0xffff, DSPInterpreter::ret, nop, 1, 0, {}, NULL, NULL},
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@ -117,8 +121,6 @@ DSPOPCTemplate opcodes[] =
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{"JLZ", 0x029d, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_VAL, 2, 1, 0, 0xffff}}, NULL, NULL},
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{"JMP", 0x029f, 0xffff, DSPInterpreter::jcc, nop, 2, 1, {{P_VAL, 2, 1, 0, 0xffff}}, NULL, NULL},
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{"DAR", 0x0004, 0xfffc, DSPInterpreter::dar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL},
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{"IAR", 0x0008, 0xfffc, DSPInterpreter::iar, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL},
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{"JRNS", 0x1700, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
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{"JRS", 0x1701, 0xff1f, DSPInterpreter::jmprcc, nop, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, NULL, NULL},
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@ -341,7 +343,7 @@ dspInstFunc epilogueTable[OPTABLE_SIZE];
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const DSPOPCTemplate *GetOpTemplate(const UDSPInstruction &inst)
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{
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for (int i = 0; i < opcodes_size; i++)
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for (u32 i = 0; i < opcodes_size; i++)
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{
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u16 mask = opcodes[i].opcode_mask;
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if (opcodes[i].size & P_EXT) {
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@ -207,21 +207,6 @@ u16 gdsp_read_cr()
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return g_dsp.cr;
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}
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// special loop step.. because exception in loop or loopi fails
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// dunno how we have to fix it
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// atm we execute this instructions directly inside the loop command
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// so it cant be interrupted by an exception.
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// TODO - we really should figure this out - on the real DSP, exception inside
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// loop should work. Think through the stack management and how it works
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// with exceptions and in loops.
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void gdsp_loop_step()
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{
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g_dsp.err_pc = g_dsp.pc;
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u16 opc = dsp_fetch_code();
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ComputeInstruction(UDSPInstruction(opc));
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}
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void gdsp_step()
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{
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g_dsp.step_counter++;
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@ -59,7 +59,7 @@
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#define DSP_REG_AXL0 0x18
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#define DSP_REG_AXL1 0x19
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#define DSP_REG_AXH0 0x1A // SMP_R accel
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#define DSP_REG_AXH0 0x1a // SMP_R accel
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#define DSP_REG_AXH1 0x1b // SMP_L accel
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#define DSP_REG_ACC0 0x1c // accumulator (global)
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