mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2025-03-14 04:19:29 +00:00
A bunch more WIP JIT work.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@1779 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
magumagu9
parent
3a3fd721d1
commit
6ad44fd470
@ -245,6 +245,13 @@ InstLoc IRBuilder::FoldZeroOp(unsigned Opcode, unsigned extra) {
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GRegCache[extra] = EmitZeroOp(LoadGReg, extra);
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return GRegCache[extra];
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}
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if (Opcode == LoadFReg) {
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// Reg load folding: if we already loaded the value,
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// load it again
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if (!FRegCache[extra])
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FRegCache[extra] = EmitZeroOp(LoadFReg, extra);
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return FRegCache[extra];
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}
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if (Opcode == LoadCarry) {
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if (!CarryCache)
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CarryCache = EmitZeroOp(LoadGReg, extra);
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@ -270,6 +277,14 @@ InstLoc IRBuilder::FoldUOp(unsigned Opcode, InstLoc Op1, unsigned extra) {
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GRegCacheStore[extra] = EmitUOp(StoreGReg, Op1, extra);
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return GRegCacheStore[extra];
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}
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if (Opcode == StoreFReg) {
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FRegCache[extra] = Op1;
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if (FRegCacheStore[extra]) {
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*FRegCacheStore[extra] = 0;
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}
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FRegCacheStore[extra] = EmitUOp(StoreFReg, Op1, extra);
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return FRegCacheStore[extra];
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}
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if (Opcode == StoreCarry) {
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CarryCache = Op1;
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if (CarryCacheStore) {
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@ -286,6 +301,10 @@ InstLoc IRBuilder::FoldUOp(unsigned Opcode, InstLoc Op1, unsigned extra) {
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CRCacheStore[extra] = EmitUOp(StoreCR, Op1, extra);
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return CRCacheStore[extra];
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}
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if (Opcode == CompactMRegToPacked) {
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if (getOpcode(*Op1) == ExpandPackedToMReg)
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return getOp1(Op1);
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}
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return EmitUOp(Opcode, Op1, extra);
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}
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@ -441,6 +460,8 @@ InstLoc IRBuilder::FoldInterpreterFallback(InstLoc Op1, InstLoc Op2) {
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for (unsigned i = 0; i < 32; i++) {
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GRegCache[i] = 0;
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GRegCacheStore[i] = 0;
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FRegCache[i] = 0;
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FRegCacheStore[i] = 0;
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}
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CarryCache = 0;
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CarryCacheStore = 0;
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@ -610,9 +631,10 @@ static X64Reg fregFindFreeReg(RegInfo& RI) {
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for (unsigned i = 0; i < FRegAllocSize; i++)
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if (RI.fregs[FRegAllocOrder[i]] == 0)
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return FRegAllocOrder[i];
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// XMM0/1 are scratch, so we don't allocate it
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fregSpill(RI, XMM7);
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return XMM7;
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static unsigned nextReg = 0;
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X64Reg reg = FRegAllocOrder[nextReg++ % FRegAllocSize];
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fregSpill(RI, reg);
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return reg;
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}
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static OpArg regLocForInst(RegInfo& RI, InstLoc I) {
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@ -1016,10 +1038,12 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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case SExt16:
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case BSwap32:
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case BSwap16:
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case Cntlzw:
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case DupSingleToMReg:
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case DoubleToSingle:
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case ExpandPackedToMReg:
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case CompactMRegToPacked:
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case FPNeg:
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if (thisUsed)
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regMarkUse(RI, I, getOp1(I), 1);
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break;
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@ -1062,6 +1086,9 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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case ICmpSgt:
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case FSMul:
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case FSAdd:
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case FPAdd:
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case FPMul:
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case FPSub:
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case InsertDoubleInMReg:
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if (thisUsed) {
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regMarkUse(RI, I, getOp1(I), 1);
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@ -1237,6 +1264,17 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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regNormalRegClear(RI, I);
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break;
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}
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case Cntlzw: {
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if (!thisUsed) break;
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X64Reg reg = regUReg(RI, I);
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Jit->MOV(32, R(ECX), Imm32(63));
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Jit->BSR(32, reg, regLocForInst(RI, getOp1(I)));
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Jit->CMOVcc(32, reg, R(ECX), CC_Z);
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Jit->XOR(32, R(reg), Imm8(31));
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RI.regs[reg] = I;
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regNormalRegClear(RI, I);
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break;
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}
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case And: {
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if (!thisUsed) break;
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regEmitBinInst(RI, I, &Jit64::AND);
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@ -1447,6 +1485,17 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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fregNormalRegClear(RI, I);
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break;
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}
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case FPNeg: {
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if (!thisUsed) break;
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X64Reg reg = fregFindFreeReg(RI);
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Jit->MOVAPD(reg, fregLocForInst(RI, getOp1(I)));
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static const u32 GC_ALIGNED16(psSignBits[4]) =
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{0x80000000, 0x80000000};
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Jit->PXOR(reg, M((void*)&psSignBits));
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RI.fregs[reg] = I;
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fregNormalRegClear(RI, I);
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break;
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}
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case LoadFReg: {
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if (!thisUsed) break;
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X64Reg reg = fregFindFreeReg(RI);
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@ -1488,6 +1537,33 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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fregNormalRegClear(RI, I);
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break;
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}
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case FPAdd: {
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if (!thisUsed) break;
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X64Reg reg = fregFindFreeReg(RI);
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Jit->MOVAPD(reg, fregLocForInst(RI, getOp1(I)));
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Jit->ADDPS(reg, fregLocForInst(RI, getOp2(I)));
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RI.fregs[reg] = I;
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fregNormalRegClear(RI, I);
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break;
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}
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case FPMul: {
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if (!thisUsed) break;
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X64Reg reg = fregFindFreeReg(RI);
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Jit->MOVAPD(reg, fregLocForInst(RI, getOp1(I)));
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Jit->MULPS(reg, fregLocForInst(RI, getOp2(I)));
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RI.fregs[reg] = I;
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fregNormalRegClear(RI, I);
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break;
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}
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case FPSub: {
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if (!thisUsed) break;
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X64Reg reg = fregFindFreeReg(RI);
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Jit->MOVAPD(reg, fregLocForInst(RI, getOp1(I)));
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Jit->SUBPS(reg, fregLocForInst(RI, getOp2(I)));
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RI.fregs[reg] = I;
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fregNormalRegClear(RI, I);
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break;
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}
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case CInt32:
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case CInt16: {
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if (!thisUsed) break;
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@ -1579,11 +1655,19 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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if (!thisUsed) break;
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// FIXME: Optimize!
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InstLoc Op = I - 1 - (*I >> 8);
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X64Reg reg = regFindFreeReg(RI);
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Jit->MOV(32, R(reg), regLocForInst(RI, Op));
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RI.regs[reg] = I;
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if (RI.IInfo[I - RI.FirstI] & 4)
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regClearInst(RI, Op);
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if (isFResult(*Op)) {
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X64Reg reg = fregFindFreeReg(RI);
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Jit->MOVAPD(reg, fregLocForInst(RI, Op));
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RI.fregs[reg] = I;
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if (RI.IInfo[I - RI.FirstI] & 4)
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fregClearInst(RI, Op);
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} else {
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X64Reg reg = regFindFreeReg(RI);
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Jit->MOV(32, R(reg), regLocForInst(RI, Op));
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RI.regs[reg] = I;
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if (RI.IInfo[I - RI.FirstI] & 4)
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regClearInst(RI, Op);
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}
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break;
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}
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case Nop: break;
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@ -41,6 +41,7 @@ namespace IREmitter {
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SExt16,
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BSwap32,
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BSwap16,
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Cntlzw, // Count leading zeros
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Load8, // These loads zext
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Load16,
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Load32,
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@ -143,19 +144,26 @@ namespace IREmitter {
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ForceToDouble,
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ForceToMReg,
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#endif
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FResult_Start,
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LoadSingle,
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LoadDouble,
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LoadPaired, // This handles quantizers itself
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StorePaired,
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DoubleToSingle,
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DupSingleToMReg,
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DupSingleToPacked,
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InsertDoubleInMReg,
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ExpandPackedToMReg,
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CompactMRegToPacked,
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LoadFReg,
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StoreFReg,
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FSMul,
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FSAdd,
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FPAdd,
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FPMul,
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FPSub,
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FPNeg,
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FResult_End,
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StorePaired,
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StoreFReg,
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// "Trinary" operators
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// FIXME: Need to change representation!
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@ -189,37 +197,9 @@ namespace IREmitter {
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return getOpcode(i) >= CInt16 && getOpcode(i) <= CInt32;
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}
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unsigned inline isUnary(Inst i) {
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return getOpcode(i) >= SExt8 && getOpcode(i) <= BSwap16;
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}
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unsigned inline isBinary(Inst i) {
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return getOpcode(i) >= Add && getOpcode(i) <= ICmpCRUnsigned;
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}
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unsigned inline isMemLoad(Inst i) {
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return getOpcode(i) >= Load8 && getOpcode(i) <= Load32;
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}
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unsigned inline isMemStore(Inst i) {
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return getOpcode(i) >= Store8 && getOpcode(i) <= Store32;
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}
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unsigned inline isRegLoad(Inst i) {
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return getOpcode(i) >= LoadGReg && getOpcode(i) <= LoadCR;
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}
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unsigned inline isRegStore(Inst i) {
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return getOpcode(i) >= LoadGReg && getOpcode(i) <= LoadCR;
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}
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unsigned inline isBranch(Inst i) {
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return getOpcode(i) >= BranchUncond &&
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getOpcode(i) <= BranchCond;
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}
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unsigned inline isInterpreterFallback(Inst i) {
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return getOpcode(i) == InterpreterFallback;
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unsigned inline isFResult(Inst i) {
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return getOpcode(i) > FResult_Start &&
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getOpcode(i) < FResult_End;
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}
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InstLoc inline getOp1(InstLoc i) {
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@ -360,6 +340,9 @@ namespace IREmitter {
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InstLoc EmitSExt8(InstLoc op1) {
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return FoldUOp(SExt8, op1);
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}
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InstLoc EmitCntlzw(InstLoc op1) {
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return FoldUOp(Cntlzw, op1);
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}
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InstLoc EmitICmpCRSigned(InstLoc op1, InstLoc op2) {
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return FoldBiOp(ICmpCRSigned, op1, op2);
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}
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@ -405,6 +388,9 @@ namespace IREmitter {
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InstLoc EmitDupSingleToMReg(InstLoc val) {
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return FoldUOp(DupSingleToMReg, val);
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}
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InstLoc EmitDupSingleToPacked(InstLoc val) {
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return FoldUOp(DupSingleToPacked, val);
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}
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InstLoc EmitInsertDoubleInMReg(InstLoc val, InstLoc reg) {
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return FoldBiOp(InsertDoubleInMReg, val, reg);
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}
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@ -420,6 +406,18 @@ namespace IREmitter {
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InstLoc EmitFSAdd(InstLoc op1, InstLoc op2) {
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return FoldBiOp(FSAdd, op1, op2);
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}
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InstLoc EmitFPAdd(InstLoc op1, InstLoc op2) {
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return FoldBiOp(FPAdd, op1, op2);
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}
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InstLoc EmitFPMul(InstLoc op1, InstLoc op2) {
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return FoldBiOp(FPMul, op1, op2);
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}
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InstLoc EmitFPSub(InstLoc op1, InstLoc op2) {
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return FoldBiOp(FPSub, op1, op2);
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}
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InstLoc EmitFPNeg(InstLoc op1) {
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return FoldUOp(FPNeg, op1);
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}
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InstLoc EmitDoubleToSingle(InstLoc op1) {
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return FoldUOp(DoubleToSingle, op1);
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}
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@ -439,6 +437,8 @@ namespace IREmitter {
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for (unsigned i = 0; i < 32; i++) {
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GRegCache[i] = 0;
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GRegCacheStore[i] = 0;
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FRegCache[i] = 0;
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FRegCacheStore[i] = 0;
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}
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CarryCache = 0;
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CarryCacheStore = 0;
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@ -458,6 +458,8 @@ namespace IREmitter {
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InstLoc curReadPtr;
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InstLoc GRegCache[32];
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InstLoc GRegCacheStore[32];
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InstLoc FRegCache[32];
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InstLoc FRegCacheStore[32];
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InstLoc CarryCache;
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InstLoc CarryCacheStore;
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InstLoc CRCache[8];
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@ -179,39 +179,32 @@
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void Jit64::subfic(UGeckoInstruction inst)
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{
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if(Core::g_CoreStartupParameter.bJITOff || Core::g_CoreStartupParameter.bJITIntegerOff)
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{Default(inst); return;} // turn off from debugger
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INSTRUCTION_START;
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int a = inst.RA, d = inst.RD;
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gpr.FlushLockX(ECX);
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gpr.Lock(a, d);
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gpr.LoadToX64(d, a == d, true);
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int imm = inst.SIMM_16;
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MOV(32, R(EAX), gpr.R(a));
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NOT(32, R(EAX));
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ADD(32, R(EAX), Imm32(imm + 1));
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MOV(32, gpr.R(d), R(EAX));
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//GenerateCarry(ECX);
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gpr.UnlockAll();
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gpr.UnlockAllX();
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// This instruction has no RC flag
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Default(inst);
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return;
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// FIXME: Disabling until I figure out subfcx
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IREmitter::InstLoc val, test, c;
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c = ibuild.EmitIntConst(inst.SIMM_16);
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val = ibuild.EmitSub(c, ibuild.EmitLoadGReg(inst.RA));
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ibuild.EmitStoreGReg(val, inst.RD);
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test = ibuild.EmitICmpUgt(val, c);
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ibuild.EmitStoreCarry(test);
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}
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void Jit64::subfcx(UGeckoInstruction inst)
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{
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INSTRUCTION_START;
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Default(inst);
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return;
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/*
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u32 a = m_GPR[_inst.RA];
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u32 b = m_GPR[_inst.RB];
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m_GPR[_inst.RD] = b - a;
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SetCarry(a == 0 || Helper_Carry(b, 0-a));
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if (_inst.OE) PanicAlert("OE: subfcx");
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if (_inst.Rc) Helper_UpdateCR0(m_GPR[_inst.RD]);
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*/
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// FIXME: Figure out what the heck is going wrong here...
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if (inst.OE) PanicAlert("OE: subfcx");
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IREmitter::InstLoc val, test, lhs, rhs;
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lhs = ibuild.EmitLoadGReg(inst.RB);
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rhs = ibuild.EmitLoadGReg(inst.RA);
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val = ibuild.EmitSub(lhs, rhs);
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ibuild.EmitStoreGReg(val, inst.RD);
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test = ibuild.EmitICmpUgt(rhs, lhs);
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ibuild.EmitStoreCarry(test);
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if (inst.Rc)
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ComputeRC(ibuild, val);
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}
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void Jit64::subfex(UGeckoInstruction inst)
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@ -394,33 +387,14 @@
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void Jit64::rlwnmx(UGeckoInstruction inst)
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{
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if(Core::g_CoreStartupParameter.bJITOff || Core::g_CoreStartupParameter.bJITIntegerOff)
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{Default(inst); return;} // turn off from debugger
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INSTRUCTION_START;
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int a = inst.RA, b = inst.RB, s = inst.RS;
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if (gpr.R(a).IsImm())
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{
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Default(inst);
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return;
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}
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u32 mask = Helper_Mask(inst.MB, inst.ME);
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gpr.FlushLockX(ECX);
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gpr.Lock(a, b, s);
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MOV(32, R(EAX), gpr.R(s));
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MOV(32, R(ECX), gpr.R(b));
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AND(32, R(ECX), Imm32(0x1f));
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ROL(32, R(EAX), R(ECX));
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AND(32, R(EAX), Imm32(mask));
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MOV(32, gpr.R(a), R(EAX));
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gpr.UnlockAll();
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gpr.UnlockAllX();
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INSTRUCTION_START
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unsigned mask = Helper_Mask(inst.MB, inst.ME);
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IREmitter::InstLoc val = ibuild.EmitLoadGReg(inst.RS);
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val = ibuild.EmitRol(val, ibuild.EmitLoadGReg(inst.RB));
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val = ibuild.EmitAnd(val, ibuild.EmitIntConst(mask));
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ibuild.EmitStoreGReg(val, inst.RA);
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if (inst.Rc)
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{
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MOV(32, R(EAX), gpr.R(a));
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CALL((u8*)asm_routines.computeRc);
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}
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ComputeRC(ibuild, val);
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}
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void Jit64::negx(UGeckoInstruction inst)
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@ -509,30 +483,9 @@
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// count leading zeroes
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void Jit64::cntlzwx(UGeckoInstruction inst)
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{
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if(Core::g_CoreStartupParameter.bJITOff || Core::g_CoreStartupParameter.bJITIntegerOff)
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{Default(inst); return;} // turn off from debugger
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INSTRUCTION_START;
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int a = inst.RA;
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int s = inst.RS;
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if (gpr.R(a).IsImm() || gpr.R(s).IsImm() || s == a)
|
||||
{
|
||||
Default(inst);
|
||||
return;
|
||||
}
|
||||
gpr.Lock(a,s);
|
||||
gpr.LoadToX64(a,false);
|
||||
BSR(32, gpr.R(a).GetSimpleReg(), gpr.R(s));
|
||||
FixupBranch gotone = J_CC(CC_NZ);
|
||||
MOV(32, gpr.R(a), Imm32(63));
|
||||
SetJumpTarget(gotone);
|
||||
XOR(32, gpr.R(a), Imm8(0x1f)); // flip order
|
||||
gpr.UnlockAll();
|
||||
|
||||
IREmitter::InstLoc val = ibuild.EmitLoadGReg(inst.RS);
|
||||
val = ibuild.EmitCntlzw(val);
|
||||
ibuild.EmitStoreGReg(val, inst.RA);
|
||||
if (inst.Rc)
|
||||
{
|
||||
MOV(32, R(EAX), gpr.R(a));
|
||||
CALL((u8*)asm_routines.computeRc);
|
||||
// TODO: Check PPC manual too
|
||||
}
|
||||
ComputeRC(ibuild, val);
|
||||
}
|
||||
|
||||
@ -88,8 +88,10 @@ void Jit64::lXz(UGeckoInstruction inst)
|
||||
IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_16);
|
||||
if (inst.RA)
|
||||
addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA));
|
||||
if (inst.OPCD & 1)
|
||||
ibuild.EmitStoreGReg(addr, inst.RA);
|
||||
IREmitter::InstLoc val;
|
||||
switch (inst.OPCD)
|
||||
switch (inst.OPCD & -2)
|
||||
{
|
||||
case 32: val = ibuild.EmitLoad32(addr); break; //lwz
|
||||
case 40: val = ibuild.EmitLoad16(addr); break; //lhz
|
||||
|
||||
@ -159,70 +159,31 @@
|
||||
add a,b,a
|
||||
*/
|
||||
|
||||
//There's still a little bit more optimization that can be squeezed out of this
|
||||
void Jit64::tri_op(int d, int a, int b, bool reversible, void (XEmitter::*op)(X64Reg, OpArg))
|
||||
{
|
||||
fpr.Lock(d, a, b);
|
||||
|
||||
if (d == a)
|
||||
{
|
||||
fpr.LoadToX64(d, true);
|
||||
(this->*op)(fpr.RX(d), fpr.R(b));
|
||||
}
|
||||
else if (d == b && reversible)
|
||||
{
|
||||
fpr.LoadToX64(d, true);
|
||||
(this->*op)(fpr.RX(d), fpr.R(a));
|
||||
}
|
||||
else if (a != d && b != d)
|
||||
{
|
||||
//sources different from d, can use rather quick solution
|
||||
fpr.LoadToX64(d, false);
|
||||
MOVAPD(fpr.RX(d), fpr.R(a));
|
||||
(this->*op)(fpr.RX(d), fpr.R(b));
|
||||
}
|
||||
else if (b != d)
|
||||
{
|
||||
fpr.LoadToX64(d, false);
|
||||
MOVAPD(XMM0, fpr.R(b));
|
||||
MOVAPD(fpr.RX(d), fpr.R(a));
|
||||
(this->*op)(fpr.RX(d), Gen::R(XMM0));
|
||||
}
|
||||
else //Other combo, must use two temps :(
|
||||
{
|
||||
MOVAPD(XMM0, fpr.R(a));
|
||||
MOVAPD(XMM1, fpr.R(b));
|
||||
fpr.LoadToX64(d, false);
|
||||
(this->*op)(XMM0, Gen::R(XMM1));
|
||||
MOVAPD(fpr.RX(d), Gen::R(XMM0));
|
||||
}
|
||||
ForceSinglePrecisionP(fpr.RX(d));
|
||||
fpr.UnlockAll();
|
||||
}
|
||||
|
||||
void Jit64::ps_arith(UGeckoInstruction inst)
|
||||
{
|
||||
if(Core::g_CoreStartupParameter.bJITOff || Core::g_CoreStartupParameter.bJITPairedOff)
|
||||
{Default(inst); return;} // turn off from debugger
|
||||
INSTRUCTION_START;
|
||||
if (inst.Rc) {
|
||||
{
|
||||
if (inst.Rc || (inst.SUBOP5 != 21 && inst.SUBOP5 != 20 && inst.SUBOP5 != 25)) {
|
||||
Default(inst); return;
|
||||
}
|
||||
IREmitter::InstLoc val = ibuild.EmitLoadFReg(inst.FA), rhs;
|
||||
if (inst.SUBOP5 == 25)
|
||||
rhs = ibuild.EmitCompactMRegToPacked(ibuild.EmitLoadFReg(inst.FC));
|
||||
else
|
||||
rhs = ibuild.EmitCompactMRegToPacked(ibuild.EmitLoadFReg(inst.FB));
|
||||
val = ibuild.EmitCompactMRegToPacked(val);
|
||||
|
||||
switch (inst.SUBOP5)
|
||||
{
|
||||
case 18: tri_op(inst.FD, inst.FA, inst.FB, false, &XEmitter::DIVPD); break; //div
|
||||
case 20: tri_op(inst.FD, inst.FA, inst.FB, false, &XEmitter::SUBPD); break; //sub
|
||||
case 21: tri_op(inst.FD, inst.FA, inst.FB, true, &XEmitter::ADDPD); break; //add
|
||||
case 23://sel
|
||||
Default(inst);
|
||||
case 20:
|
||||
val = ibuild.EmitFPSub(val, rhs);
|
||||
break;
|
||||
case 24://res
|
||||
Default(inst);
|
||||
case 21:
|
||||
val = ibuild.EmitFPAdd(val, rhs);
|
||||
break;
|
||||
case 25: tri_op(inst.FD, inst.FA, inst.FC, true, &XEmitter::MULPD); break; //mul
|
||||
default:
|
||||
_assert_msg_(DYNA_REC, 0, "ps_arith WTF!!!");
|
||||
case 25:
|
||||
val = ibuild.EmitFPMul(val, rhs);
|
||||
}
|
||||
val = ibuild.EmitExpandPackedToMReg(val);
|
||||
ibuild.EmitStoreFReg(val, inst.FD);
|
||||
}
|
||||
|
||||
void Jit64::ps_sum(UGeckoInstruction inst)
|
||||
@ -347,58 +308,37 @@
|
||||
//TODO: add optimized cases
|
||||
void Jit64::ps_maddXX(UGeckoInstruction inst)
|
||||
{
|
||||
if(Core::g_CoreStartupParameter.bJITOff || Core::g_CoreStartupParameter.bJITPairedOff)
|
||||
{Default(inst); return;} // turn off from debugger
|
||||
INSTRUCTION_START;
|
||||
if (inst.Rc) {
|
||||
if (inst.Rc || (inst.SUBOP5 != 28 && inst.SUBOP5 != 29 && inst.SUBOP5 != 30)) {
|
||||
Default(inst); return;
|
||||
}
|
||||
int a = inst.FA;
|
||||
int b = inst.FB;
|
||||
int c = inst.FC;
|
||||
int d = inst.FD;
|
||||
fpr.Lock(a,b,c,d);
|
||||
|
||||
MOVAPD(XMM0, fpr.R(a));
|
||||
|
||||
IREmitter::InstLoc val = ibuild.EmitLoadFReg(inst.FA), op2, op3;
|
||||
val = ibuild.EmitCompactMRegToPacked(val);
|
||||
switch (inst.SUBOP5)
|
||||
{
|
||||
case 14: //madds0
|
||||
MOVDDUP(XMM1, fpr.R(c));
|
||||
MULPD(XMM0, R(XMM1));
|
||||
ADDPD(XMM0, fpr.R(b));
|
||||
case 28: {//msub
|
||||
op2 = ibuild.EmitCompactMRegToPacked(ibuild.EmitLoadFReg(inst.FC));
|
||||
val = ibuild.EmitFPMul(val, op2);
|
||||
op3 = ibuild.EmitCompactMRegToPacked(ibuild.EmitLoadFReg(inst.FB));
|
||||
val = ibuild.EmitFPSub(val, op3);
|
||||
break;
|
||||
case 15: //madds1
|
||||
MOVAPD(XMM1, fpr.R(c));
|
||||
SHUFPD(XMM1, R(XMM1), 3); // copy higher to lower
|
||||
MULPD(XMM0, R(XMM1));
|
||||
ADDPD(XMM0, fpr.R(b));
|
||||
break;
|
||||
case 28: //msub
|
||||
MULPD(XMM0, fpr.R(c));
|
||||
SUBPD(XMM0, fpr.R(b));
|
||||
break;
|
||||
case 29: //madd
|
||||
MULPD(XMM0, fpr.R(c));
|
||||
ADDPD(XMM0, fpr.R(b));
|
||||
break;
|
||||
case 30: //nmsub
|
||||
MULPD(XMM0, fpr.R(c));
|
||||
SUBPD(XMM0, fpr.R(b));
|
||||
XORPD(XMM0, M((void*)&psSignBits));
|
||||
break;
|
||||
case 31: //nmadd
|
||||
MULPD(XMM0, fpr.R(c));
|
||||
ADDPD(XMM0, fpr.R(b));
|
||||
XORPD(XMM0, M((void*)&psSignBits));
|
||||
break;
|
||||
default:
|
||||
_assert_msg_(DYNA_REC, 0, "ps_maddXX WTF!!!");
|
||||
//Default(inst);
|
||||
//fpr.UnlockAll();
|
||||
return;
|
||||
}
|
||||
fpr.LoadToX64(d, false);
|
||||
MOVAPD(fpr.RX(d), Gen::R(XMM0));
|
||||
ForceSinglePrecisionP(fpr.RX(d));
|
||||
fpr.UnlockAll();
|
||||
case 29: {//madd
|
||||
op2 = ibuild.EmitCompactMRegToPacked(ibuild.EmitLoadFReg(inst.FC));
|
||||
val = ibuild.EmitFPMul(val, op2);
|
||||
op3 = ibuild.EmitCompactMRegToPacked(ibuild.EmitLoadFReg(inst.FB));
|
||||
val = ibuild.EmitFPAdd(val, op3);
|
||||
break;
|
||||
}
|
||||
case 30: {//nmsub
|
||||
op2 = ibuild.EmitCompactMRegToPacked(ibuild.EmitLoadFReg(inst.FC));
|
||||
val = ibuild.EmitFPMul(val, op2);
|
||||
op3 = ibuild.EmitCompactMRegToPacked(ibuild.EmitLoadFReg(inst.FB));
|
||||
val = ibuild.EmitFPSub(val, op3);
|
||||
val = ibuild.EmitFPNeg(val);
|
||||
break;
|
||||
}
|
||||
}
|
||||
val = ibuild.EmitExpandPackedToMReg(val);
|
||||
ibuild.EmitStoreFReg(val, inst.FD);
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user